Abstract: A screen-oriented process is used for configuring devices in an open computer system. The computer system includes an operating system having device drivers, and the operating system can be run as a virtual machine on a virtual resource manager wherein a procedure is used to bind the device drivers of the operating system and the virtual resource manager and an attached device on a particular port of an adapter using device dependent information. The configuring process initially requires the creation of device dependent information files for a plurality of devices and device types, and these files are installed in the computer system. Each file includes adpater specific information and device specific information consolidated in a single file. The user may invoke a configuration command, and the system responds by displaying a plurality of commands such as add, change, delete and show and prompts the user to choose a command.

Abstract: An information processing apparatus is provided in which a processor is connected to a memory via address and data buses and an address bus is connected via a continuous address-specifying signal generating circuit. In a continuous access mode, the continuous address data generating circuit is responsive to an instruction signal for re-setting itself to an initial value and sequentially supplying a continuous address data to the memory's designated address. In the continuous access mode, the address bus is employed, together with the aforementioned data bus, as a data bus in a parallel fashion so that a data transfer capability can be extended.

Abstract: A pipelined parallel vector processor is disclosed. In order to increase the performance of the parallel vector processor, the present invention decreases the time required to process a pair of vectors stored in a pair of vector registers. The vector registers are subdivided into a plurality of smaller registers. A vector, stored in a vector register, comprises N elements; however, each of the smaller registers store M elements of the vector, where M is less than N. An element processor, functioning in a pipeline mode, is associated with each smaller register for processing the M elements of the vectors stored in the smaller register and generating results of the processing, the results being stored in one of the vector registers. The smaller registers of the vector registers, and their corresponding element processors, are structurally configured in a parallel fashion. The element processors and their associated smaller registers operate simultaneously.

Abstract: A circuit arrangement (adapter) for attaching a display device to a serial I/O channel is disclosed. The circuit arrangement captures a serial message of indeterminate length and places said message unit into a refresh RAM in a synchronous manner during non-display periods. The circuit arrangement includes a microprocessor whose address and data buses are coupled to a microprocessor RAM and through control circuitry to the address and data buses of a refresh RAM. Data is transferred at high speed from the serial I/O channel to the microprocessor RAM. When the microprocessor executes a read command, the microprocessor RAM is placed in a "read mode" while the refresh RAM is placed in a "write" mode. Data at the address selected in the microprocessor RAM is transferred to an identical address in the refresh RAM. Similarly, data can be transferred from the refresh RAM into the microprocessor RAM. Thus, the execution of a single command at a single address results in the selection of two RAMs.

Abstract: A microprogram processor to execute high speed memory access when an operand indicates a memory is provided. This microprogram processor comprises an instruction register for holding a unit length of an instruction code, an instruction decoder for decoding an instruction code in the register, thus generating a signal dependent upon the fact that the operand indicates a register or a memory, a microcode decoder for decoding a microcode generated from a ROM depending upon the instruction code, thus generating a noncondition memory access signal and a next instruction start condition signal, and a next instruction start condition judgement decoder connected to receive both an output from the instruction code decoder and the next instruction start condition signal to judge whether or not the next instruction start is correct. The microcode decoder further generates a conditional memory access signal when the operand indicates a memory. Thus, a memory access signal generator circuit, e.g.

Abstract: Described is an apparatus and method which allow multiple stations on a communications network to be Initial Program Loaded simultaneously from a server station. Thus, the method minimizes the time it would normally take to load the stations sequentially. Following the establishment of a program loading session between the server station and a station in the network, other stations requiring the program are allowed to participate in the session and receive any remaining portions of the program which have not yet been transmitted to the station. At the conclusion of the session, the server station retransmits, to the stations, that portion of the program which it had already transmitted at the time when the stations join the session.

Abstract: A plurality of language display control cards are provided for insertion into the motherboard of a personal computer, each card having connector means to which a CRT display and a keyboard may be connected. Each card controls its display independently of the others so that different data may be displayed on each display screen. A display control card includes a font memory for storing the digital video representations of ideographic characters of a standard code, and an ASCII memory for storing the digital video representations of ASCII characters. In addition a loadable font memory is provided for storing the digital video representations of characters which are not commonly used characters of a language but may be frequently used in a particular application. The outputs of the three memories may be serially interspersed so that the CRT may display ASCII, or ideographic characters or a mixture of both.

Abstract: A data processing apparatus for processing text, words or characters has a key entry device, a memory for saving key data from the key entry device and processing means for sequentially processing the key data stored in the memory. When a same key of the key entry device is continuously depressed, the saving of the key data into the memory is suppressed.

Abstract: An apparatus for recording a plurality of variable analog signals individually and sequentially scanned during the recording operation. The analog signals are digitized, and the digital values multiplexed into a microprocessor which uses a stored program to determine significant changes in the scanned analog input and to store only meaningful data representing a significantly changed analog input in a buffer memory for subsequent recording on a recording chart. Specifically, the apparatus provides a selection of input values to be recorded whereat the recorded input values differ by a predetermined amount with respect to the measured value or the time basis of a recording chart. The buffer memory serves to match the velocities between scanning of the inputs and the printing of the measured variables since the inputs are scanned at a rate which is much higher than the print rate of the recorder to allow a follow-up of the measured variable which provides equidistant recording of the measured values.

Abstract: An industrial I/O controller is implemented on a processor board and includes two I/O daughter boards which are mounted on and parallel to the processor board by means of connectors such that the entire system occupies only a single slot space of a VMEbus back plane. The processor board includes a VMEbus connector attached to its upper right-hand edge. First buffer circuitry, a static RAM, second buffer circuitry and an EPROM are located from right to left along the upper edge of the processor board. Two connectors for attachment of two I/O daughter boards are located in the lower part of the processor board.

Abstract: A relational database is created and queried through the use of an outliner-style text editor which permits automatic generation of data entry forms for the creation of records. Data entry and editing are simplified and errors are minimized because changes in the outline are automatically reflected in the data entry forms and thus the automatically updated records. Data retrieval is driven through the manipulation of the outline to allow simple and complex queries without utilizing a database programming language. A specialized global field is utilized in which identical field names may be repetitively inserted into several databases. In the data entry mode, a global value can be set and that value is automatically inserted into each database record containing that global field as they are created so that relations are made automatically within the various databases.

Abstract: A mapping-type data signal optimizer performs a code-point sorting function to optimize downloading of programmed symbols. A present-state list of values of programmed symbols already downloaded to a peripheral device is sorted, and a similar intended-state list of programmed symbols intended to be downloaded is likewise sorted. A search is performed to detect any commonalities that might exist between the present-state and intended-state programmed-symbol values, even under differing programmed-symbol designators. When such a commonality is detected, the intended- state designator is altered to be equal to the present-state designator; thus, that particular programmed symbol value need not be redownloaded.

Abstract: A counter/timer device includes a plurality of registers each capable of performing the function of any of a counter/timer register, a capture register and a compare register, in accordance with a command from a central processing unit, and a plurality of task registers corresponding to tasks which are to be carried out by using the above registers. Each of the task registers stores a task instruction for specifying a counter/timer register and a capture/compare register which are used in a task, and for specifying the operation mode of each of the specified registers. The task registers are scanned to successively read out the task instructions, and each of the read-out task instructions controls the operation of each of registers used in a corresponding task. Thus, tasks corresponding to the task instructions are all carried out at once.

Abstract: A multiprocessor computing system includes a plurality of processors which are connected to each other through a system bus. Each processor comprises a processing unit, a local memory and an interface unit, which are interconnected so that the processing unit of any processor has access to both its own local memory and the local memory of any other processor through such interface unit and the system bus for concurrently writing into all of the local memories, information identified by a destination code as a global data.

Abstract: An information processing system comprises at least one arithmetic processing unit operating under the control of a microprogram and a system control unit which exchanges information with the arithmetic processing unit. The system control unit is not required to perform distinction processing between one source of interruption, for example a fault notice, and another source of interruption, for example a clock synchronization demand.

Abstract: A method of up-dating a cache (10) backed by a main memory (12). The cache is used as an intermediate high-speed memory between the main memory and a data processing unit (14). A burst mode request is for multiple words (k through n) included in an m-word line of data words (1 through m). The transfer takes place by first determining if the requested data words (k through n) reside in the cache. If they do, then the requested words (k through n) are transferred from the cache to the data processing unit. If they do not, then the requested words (k through n) are transferred simultaneously from the main memory both to the cache and to the data processing unit to thereby update the cache.

Abstract: A process for transitioning a hierarchical input database to create a hierarchical output database. The processing occurs generally in two stages. During the first stage, information contained in user-specified driver tables is utilized to extract only pertinent data from the input database and thereby produce intermediate data in a form accessible by the second stage. During the second stage, information from the driver tables is applied to the intermediate data to map this data to the required output form representative of the hierarchical output database. With this processing approach, the driver tables are derived and then maintained independently of underlying software that executes under control of the driver tables. A database conversion is efficiently effected by preparing the driver tables and then invoking execution of the common software embodying the extracting and mapping subprocesses.

Abstract: In an array of processing cells arranged as a single instruction multiple data processor, each processing cell contains logic which enables the cell to determine individually whether it will perform an arithmetic or logic operation or be in an idle condition. This cell-level logic includes a control register whose contents determine the operating or idle condition of the cell, and also includes PUSH/POP/COMPLEMENT stack mechanisms to represent multiple complex levels of conditions, and mechanisms to load the results of a cell-level test or arithmetic instruction into the control register, providing data-dependent control at the cell level.

Abstract: A cache memory system having an improved area addressing scheme for rewriting is disclosed. The cache memory system comprises a cache memory having a plurality of memory areas, a first detection circuit for designating the least recently accessed area by a CPU, a second detection circuit for detecting that the least recently accessed memory area is not designated and a control circuit for forcibly selecting a predetermined one memory area for rewriting when the least recently accessed memory area is not designated.

Abstract: A multiprocessing system and method for multiprocessing is disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made.