Abstract: An apparatus for document browsing, specifically for document retrieval systems. The browsing apparatus enables users to see multiple document pages on the same screen at the same time in a first mode and to see a bundle of pages on a screen in a second mode. The images shown on the screen are produced internally according to the user's commands. The pages may be flipped in either direction and selected pages may be marked for later printing instructions.

Abstract: A method for selecting the sizes and the ordering of the extents used to construct a file, a segment, or a virtual space of a computer system (file). The general method is defined to be any function, applied to this purpose, that, in general, attaches larger extents to the larger file addresses, and for which the selection of extent sizes is determined only by the address an extent is to reside at in the file, plus any tuning parameters. The method results in files which are mostly contiguous, and that stay mostly contiguous, irrespective of any growth or shrinkage the file may be subjected to during its lifetime. High contiguity improves performance by permitting a compact file representation, and, for disc files, improves performance by permitting larger blocks of data to be moved to or from the disc device, and by minimizing head seeks.

Abstract: A pulse generating apparatus comprises a command memory for storing a command which includes an output value at each time point of a pulse to be generated. The command is executed by a sequencer and the output value is supplied to an output memory from the sequencer, to be stored therein. The output memory supplies the output value to an output circuit, in synchronism with reference time point signals, and the output circuit forms the pulse from this output value.

Abstract: An electronic device comprising a state machine is coupled between the ROM and its socket. When armed by an arming sequence, the device responds to an address from a microprocessor during a reset operation to modify the output of the ROM. The modified output causes a jump to a routine in RAM rather than a jump in an initialization routine in the ROM. This enables a user to change the microprocessor's addressing mode from protected to real without a complete initialization of the system. Arming of the device and reset of microprocessor is caused by a protected mode routine, and after reset the mircroprocessor processes a real mode routine.

Abstract: The present invention relates to a programmable microcomputer or microprocessor device with associated memory and telephone circuitry designed to be operated in most circumstances through a standard telephone 12-key keypad input. The microcomputer device of the present invention, which includes the primary microprocessor operated in conjunction with other computer elements, including memory, has the overall appearance of a telephone. The primary microprocessor of the invention consists of a central processing unit and associated memory and includes enhanced integrity features. The device delivers data processing capabilities and services through an ordinary telephone instrument.

Abstract: An improved memory control and refresh apparatus as shown. For memory read operations, the read only memory and the random access memory are controlled by the NCSROM conductor (41) and the NCSRAM conductor (40), respectively, so that the read only memory and the random access memory do not compete for control of the data bus (20). However, the NCSRAM conductor (40) is not used to control the random access memory during write operations. Therefore, when transferring blocks of data from the read only memory (60) to the random access memory (61,62) the NCSROM conductor (41) is active during both reading of data from the read only memory (60) and writing of the data to the random access memory (61).

Abstract: An apparatus and method are disclosed for implementing the system architectural requirement of precise interrupt reporting in a pipelined processor with multiple functional units. Since the expense of an interrupt pipeline is warranted only for those interrupts that occur frequently--specifically, those arising from virtual memory management--the apparatus utilizes an interrupt pipeline for frequently occurring interrupts, and a slower, but much less costly, software-based system for precisely reporting the remaining interrupts. The software-based system is facilitated by an instruction numbering and tracing scheme, whereby pertinent information concerning executed instructions is recorded as the instructions pass through the processor pipeline and potentially to other functional units. A software interrupt handler may use this information to isolate and precisely report an interrupt.

Abstract: A floating point instruction control mechanism which processes loads and stores in parallel with arithmetic instructions. This results from register renaming, which removes output dependencies in the instruction control mechanism and allows computations aliased to the same register to proceed in parallel.

Abstract: The concurrent sorting apparatus and method pertains to a pipelined and concurrent sorting engine that can operate with single or double-ported host memory and, specifically, sort data with serial input and output. The apparatus is composed of stages that can vary in count to provide faster sort convergence or lower complexity. Each stage includes a first comparator and a storage. The first comparator of each stage is responsive to the value of an input element for storing that element in the storage if, for example, the input element value is equal to or greater than the value of the last stored element in that stage and for passing on to the next stage if the incoming element value is less than the value of the last stored element. The output from the storage of the adjacent stages are compared for passing down from stage to stage to the output the element having for the example the lesser value.

Abstract: A cache memory addressable by both physical and virtual addresses includes a cach data memory (64) and a tag memory (66). The tag memory (66) is comprised of a virtual tag memory (68) and a physical tag memory (70). The physical and virtual tag memories are both addressable by the least significant bits (LSB) of the address signal to output tag portions of addresses associated with data stored in the cache data memory (64). A switch (78) selects between the outputs from the memories (68) and (70) under control of an arbitration unit (88). The arbitration unit (88) distinguishes between virtual or physical addresses input thereto. A comparator (100) compares the selected tag portion with the tag portion of the received address to determine if a match exists. If a match exists, the output of the cache data memory is selected with a switch (84).

Abstract: A data processing system is described in which the available technology is used to provide high performance. The high performance is achieved by having a four-level pipeline for the central processing system, a simplified instruction set and an interface with the coprocessor unit that has a simple and efficient interface with the normal instruction execution. The apparatus implementing the central processing system is closely connected to the instruction set. A discussion of the implementation of the data processing system is provided.

Abstract: The present invention relates to a programmable microcomputer or microprocessor device with associated memory designed to be operated in most circumstances through a standard telephone 12-key keypad input as augmented by four programmable function keys. The microcomputer device of the present invention, which includes the primary microprocessor operated in conjunction with other computer elements, including memory, has the overall appearance of a telephone. The primary microprocessor of the invention consists of a central processing unit and associated memory and includes enhanced integrity features.

Abstract: Stages of a graphics data processing pipeline are interconnected by a common bus for conveying data and arbitration signals to and from each stage. Each data transmitting stage arbitrates for and acquires control of the bus when it has output data to transmit to an addressable storage location within a next stage. Each pipeline stage other than a first stage generates a BUSY bit indicating whether it is processing data or awaiting new input data from its preceding stage. When one pipeline stage has output data to transmit to a next pipeline stage, the transmitting stage periodically polls the receiving stage by acquiring control of the bus and placing on the bus a particular address associated with the next stage. Whenever the next stage detects the presence of the particular address on the bus, it places its BUSY bit on the data lines of the bus.

Abstract: A method for managing data in a data storage hierarchy, and a data storage hierarchy suitable therefor, is disclosed. The data storage hierarchy includes an optical library and separate manually operated shelf storage. The optical library includes at least one optical disk drive and a plurality of storage cells for the storage of optical disks. The optical library also includes automatic means for transferring optical disks from the storage cells to the optical disk drives in the library. The host processor, upon determining that particular data is required to be stored in the optical library, first checks to determine if the optical disks in the optical library currently have the capacity for the storage of such data. If the capacity exists in the optical library there is no problem and the data is stored therein.

Abstract: An electrotactile vocoder for persons having impaired hearing in which electrical stimulation is applied to a multiplicity of electrodes in contact with either side of each finger so as to electrically stimulate the digital nerves of the user under the control of stimulator circuitry which is in turn controlled by processing circuitry for a speech signal received by a directional microphone worn on the ear of the user. The speech processor is suitably of the type described in U.S. Pat. No. 4,441,202 Tong et al. modified to cause stimulation of the digital nerves via the eight finger electrodes and a common electrode held in contact with the wrist of the user.

Abstract: A method for providing a plurality of external IC (Integrated Circuit) cartridges to an electronic device having a CPU (Central Processing Unit) is disclosed. The IC cartridge includes first and second connectors. The first is connected to the electronic device and the second is connected to another IC cartridge and enables a plurality of IC cartridges to be connected to one electronic device. Each of the IC cartridges has a selector which selects an individual memory address. Either the IC cartridge or the electronic device has a label on which the method for setting the memory address is indicated.

Abstract: A process for the modification of device configuration in a computer system is designed to be easy-to-use by the user of the computer system yet allow the user flexibility in the specification of device configuration. The computer system stores parameter values of various default devices and devices already installed in the computer system. When the user invokes an "ADDDEV" command, the system prompts the user to enter one of a plurality of commands such as add, change or delete. Assuming the user enters the add command, the system prompts the user to enter the name of a default device or a similar device already installed in the system. When that information is entered by the user, the system determines from the stored parameters for the default or similar device which parameters must be re-specified by the user for the device to be added to the system. The system then prompts the user to enter only those parameters requiring respecification.

Abstract: Image data objects are accumulated in a relatively rapid access data buffer, such as a combination of main memory and a rapid access magnetic DASD. An optical disk recorder having a record medium with a plurality of addressable sectors each capable of storing a predetermined number of the VTOC entries receives the accumulated data objects along with the associated VTOC entries in a single access whenever the number of accumulated data objects is an inegral number of said predetermined number. A lower threshold for a minimal number of data bytes of the accumulated data objects may be required before such single access data recording operation is effected. An upper threshold of number of data bytes in the accumulated objects is also provided for causing the single access data transfer irrespective of the number of objects being an integral number of said predetermined number. The invention is advantageously practiced with a write-once, read-many record medium.

Abstract: A system for implementing a repeater interlock scheme between a first and a second bus utilizes two repeaters. The first repeater coupled to the first bus includes an interlock state bit which is set upon the acceptance of an interlock transaction from a processor. No further interlock transactions will be accepted while the interlock state bit is set. The interlock transaction is passed to a transaction buffer in the second repeater which is coupled to memory through the second bus. The transaction buffer passes the interlock data for memory to the second bus while simultaneously loading a one deep interlock buffer. A confirmation is sent from the memory back to the transaction buffer. If the confirmation is interlock busy, then the interlock transaction is retried from the interlock buffer thus allowing the transaction buffer to process other commands. The interlock buffer waits for an unlock write signal before retrying an interlock transaction thus alleviating congestion on the second bus.

Abstract: This invention relates to a data processor with pipelining system, which is provided with at least two stages having working stackpointer respectively, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and each working stackpointer corresponding to each stage is renewed synchronizing with pipelining processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to corresponding working stackpointers synchronizing with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.