Abstract: A microcomputer prioritizes data operand requests and instruction prefetch requests. Such prioritizing is established by established criteria. The established priority is altered upon the occurrence of a signal. The signal indicates a certain type of data requests. This data request type is deemed to have a higher priority than is typical for a data request. Consequently, in response to receiving the signal which indicates this data request type, the priority is altered so as to be more inclined to perform the data request. This is particularly useful when performing numerous consecutive data operations, such as a co-processor interface operation.

Abstract: The transition table size and table-driven locking facilities if reduced by decomposing lock states into canonical states and canonical-actual maps, mapping actual processors to canonical processors, looking up a transition in a table which contains a new canonical state, notify bits and a canonical-canonical map, permuting the canonical-actual map using the canonical-canonical map, and permuting the notify bits using the original canonical-actual map.

Abstract: Cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of the cache are equal in capacity. The two parts of the cache, designated I-Cache and O-Cache, are semi-independent in their operation and include arrangements for effecting synchronized searches, they can accommodate up to three separate operations substantially simultaneously. Each cache unit has a directory and a data array with the directory and data array being separately addressable. Each cache unit may be subjected to a primary and to one or more secondary concurrent uses with the secondary uses prioritized.

Abstract: A data processing system having a main processing unit, a memory subsystem, and a co-processor selectively connectable to said memory subsystem through an Input/Output Channel Controller which includes a control means for arbitrating access to the I/O Bus among the co-processor and the other I/O devices connected to the Bus. Since the co-processor runs programs stored in the memory subsystem, there is a tendency for the co-processor to monopolize the bus with instruction fetch cycles, thereby excluding other I/O devices from access to the bus. The control means for arbitrating responds to requests on the basis of a linear priority scheme in which the co-processor has the lowest priority. Each device, except the co-processor, is permitted to keep control of the bus until it voluntarily relinquishes it. The co-processor, on the other hand, relinquishes control of the bus in response to a request for access by any higher operator.

Abstract: A processor forms part of a computer network wherein the processor, designated as the User Interface Processor, operates to initialize and maintain and communicate to remote diagnostic terminals for purposes of confirming integrity of the system and also for finding the location of any faults or problems in the system. The User Interface Processor involves a microprocessor unit working in conjunction with a serial communications controller, random access memory and read only memory memories, a communications input/output (I/O) system, a multiple set of timer units and a priority interrupt controller. The User Interface Processor provides interfaces to a power control card unit, an I/O subsystem (of data link processors), and a remote terminal for diagnostic intercommunication.

Abstract: In order to feed to pluggable electronic modules addresses for an address-controlled data exchange with a control unit, a module code characterizing the type of module is stored in each module in a first memory. A plug location code is further communicated to each module via a transmitter. During an initialization phase, all modules are addressed via the plug location codes and communicate to the control unit their respective module codes. The control unit thereupon communicates the relevant addresses to the modules by addressing the plug location codes, which then are used for further data exchange. The relevant address for each module is stored in a second memory of each module.

Abstract: A maintenance processor forms part of a computer network wherein the processor (also designated as the User Interface Processor) operates to initialize and maintain and communicate to remote diagnostic terminals for purposes of confirming integrity of the system and also for displaying data for locating any faults or problems in the network. The maintenance subsystem initiates start-up and self-test routines in a sequenced order for establishing the integrity of the units in the network. The subsystem includes means for testing two types of subsystems, that is, one having I/O controllers with self-test capability and another subsystem having I/O controllers without self-test capability. The UIP provides means for complete control of the network. It can interface the network to a remote service center where all operations such as power-up and initialization can be also effectuated.

Abstract: A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.

Abstract: For receiving or transmitting binary signals appearing serially on a plurality of lines to and from a processing device containing a microcomputer or microprocessor, the signal receiving lines carrying the serially appearing binary signals are connected via individual flip-flops to the input side of the microcomputer or microprocessor and signal output lines are connected via individual flip-flops to the output of the microcomputer or microprocessor. In the processing device, the serially appearing binary signals are received into memories or registers as parallel signals for processing and, after a prescribed plurality has been received, are forwarded to the receiving registers for subsequent processing. The processed parallel signals are then reconverted into serial signals for signal transmission.

Abstract: This invention discloses a circuit for examining the value transmitted via a digital bus. A determination is made as to whether the value matches a predefined programmable value. An output indication is given for a match. In addition, this circuit may examine the transmitted value to determine whether it is within the bounds of a predefined range of values. This circuit utilizes a minimum of space and hardware components, due to its fabrication using RAM devices and a program logic array.

Abstract: For receiving and/or transmitting serially appearing binary signals to and from a processing device containing a microcomputer or microprocessor, the signal receiving lines carrying the serially appearing binary signals are connected by way of individual flip-flop elements to an input of the microcomputer or microprocessor, and signal output lines are connected by way of individual flip-flop elements to respective outputs of the microcomputer or microprocessor. In the microcomputer or microprocessor, the serial appearing binary signals are converted into parallel signals for processing, and the processed parallel signals are reconverted into serial signals for signal transmission.

Abstract: In video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

Abstract: A data storage apparatus uses a store having a nibble mode facility which allows two words to be accessed in a single extended cycle. Store access requests are held in a first-in-first-out queue in a buffer. When processing strings of data, double-read requests are alternated with pairs of write requests. A read request may be incorrectly aligned i.e. it may occur between a related pair of write requests. When an incorrectly aligned read request is detected, it is given priority so that it is executed ahead of its normal turn, and is then skipped when it is encountered during normal sequential read-out from the buffer. This allows the pair of write requests to be grouped together for execution in a single extended cycle.

Abstract: A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test apparatus coupled to the control apparatus and operates to selectively alter the operational states of the cache levels in response to commands received from a central processing unit for enabling testing of such control apparatus in addition to the other cache control areas.

Abstract: A storage control system controls the update operations on two buffer address arrays in a data processing system in which a plurality of processors are connected to a shared storage, at least one of the processors having a buffer storage. The first buffer address array is the directory of buffer storage. The second buffer address array contains the same data as that of the first buffer address array. The storage control system updates first the content of the second buffer address array then that of the first buffer address array in response to a block transfer to the buffer storage of the own processor and a store operation conducted by other processor on the shared storage. The storage control system permits to accept a new access request occurred in the own processor on condition that a block transfer to the own processor is finished and that the first buffer address array is updated in association with the block transfer.

Abstract: In a data processor having a paging system, a list is kept of the disk seek time when a page of information is brought into processor memory from a disk storage device. (Seek time is the time for moving the disk read-write head radially inward or outward to the next track that is to be accessed.) The average seek time for the pages in memory is calculated and is compared with a reference value of seek time. When the average reaches the reference, the pages in memory are reordered on the disk. This reordering takes place as the pages are bumped from memory in the normal process of paging, and the pages are relocated on the disk tracks in the physical order in which the pages were originally brought into memory. If approximately the same pages are fetched again in approximately the same sequence, the read-write head of the disk drive will be moved a shorter distance between successive disk accesses with reduced backtracking.

Abstract: A serdes device includes circuitry for loading or reading bit configurations into or out of strings of latches of variable length nk+r, where n is the number of bits in a byte, k is the number of whole bytes and r is the number of residual bits, with r being smaller than n.Under the control of a service processor (8), there is formed a ring comprised of the latches of the serializer/deserializer register (14), the latches of the string considered (3 or 4) and a selected number (n-r) of latches of an extension register (16). The bytes to be loaded are sequentially sent to register (14), starting with the byte that contains the residual bits, and n bits are shifted out after loading each successive byte, so that after k+1 shifts the desired configuration will be contained in the string. For reading the contents of a string (for example, string 3), n bits are shifted, register (14) is read out, then k shifts of n bits each are performed, with register (14) being read out after each shift.

Abstract: This circuit provides for synchronizing duplex copies of processor controllers. Either controller may be active in the simplex mode. That is, one controller is actively operating and controlling processors, while the other controller is in a standby mode. In this situation, the synchronization circuit synchronize its clock to itself. When a previously standby controller is made active, the control inputs of the standby controller are manipulated such that, the clock of the standby controller is synchronized to the already active a controller's clock. Once synchronism is achieved, the controllers are said to be operating in a synchronized duplex mode. The synchronization circuit of each controller then continuously checks to insure that the two controller copies are operating synchronously. If a non-synchronous condition is encountered by one of the synchronization circuits, the circuit that detected the lack of synchronization is repeatedly forced to a particular memory location.

Abstract: An integrated circuit device includes a data processing unit (CPU), a first read only memory (ROM) storing an applications program to be executed in the CPU, a second ROM having an address space which is addressed in common with the first ROM and storing a test program for a function diagnosis, and a test control unit. The test control unit is responsive to a test control signal externally applied in a test mode to couple the second ROM to the CPU so that the test program for setting an initial condition is executed. During the execution of the test program, the first ROM is coupled to the CPU, thereby executing applications program instructions the contents and the number of which are externally designated. Thereafter, the second ROM is coupled to the CPU so as to execute the test program for deciding a test complete condition. The execution result of the applications program instructions are compared with expected values to decide if the integrated circuit device functions normally.

Abstract: A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test control apparatus which couples to the directory error checking apparatus operates to selectively enable and disable the directory error checking circuits in response to commands received from a central processing unit so as to enable the testing of the cache directory and other portions of the cache system using common test routines.