Abstract: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming a counter doped semiconductor layer on a physically exposed and recessed surface of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The presence of the counter doped semiconductor layer isolates the source/drain regions from the semiconductor substrate and eliminates parasitic transistor formation.

Abstract: A method for forming a multi-level stack having a multi-level contact is provided. The method includes forming a multi-level stack comprising a specified number, n, of conductive layers and at least n?1 insulating layers. A via formation layer is formed over the stack. A first via is etched in the via formation layer at a first edge of the stack. A first multi-level contact is formed in the first via. For a particular embodiment, a second via may be etched in the via formation layer at a second edge of the stack and a second multi-level contact may be formed in the second via.

Abstract: A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.

Abstract: One illustrative method disclosed herein includes, among other things, forming a source/drain contact structure between two spaced-apart transistor gate structures, forming a non-uniform thickness layer of material on the upper surface of the gate cap layers and on the upper surface of the source/drain contact structure, wherein the non-uniform thickness layer of material is thicker above the gate cap layers than it is above the source/drain contact structure, forming an opening in the non-uniform thickness layer of material so as to expose at least a portion of the source/drain contact structure, and forming a V0 via that is conductively coupled to the exposed portion of the source/drain contact structure, the V0 via being at least partially positioned in the opening in the non-uniform thickness layer of material.

Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.

Abstract: Provided is a semiconductor light emitting device 1 includes a semiconductor stacked layer 2 having a light extraction surface 3a perpendicular to a stacked surface of the semiconductor stacked layer 2, a light transmissive light guide member 3 disposed on the semiconductor stacked Layer 2, a light reflective member 4 disposed on the light guide member 3, and a light reflective package 5 which has an open portion corresponding to the light extraction surface 3a and surrounds peripheral surfaces of the semiconductor stacked layer 2.

Abstract: Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a buffer layer of the semiconductor device. For instance, a semiconductor device includes a buffer layer disposed on a substrate, a channel layer disposed on the buffer layer, and a buried resistor disposed within the buffer layer. The buffer and channel layers may be formed of compound semiconductor materials such as III-V compound semiconductor materials. Utilizing the buffer layer of a compound semiconductor structure to form buried resistors provides a space-efficient design with increased integration density since the resistors do not have to occupy a large amount of space on the active surface of a semiconductor integrated circuit chip.

Abstract: A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one electrically conductive feature and forming a shield layer on the opening. A gouge is formed in the electrically conductive feature through the opening using a subtractive method during which the shield layer protects the interlevel dielectric layer from being damaged by the subtractive method. A contact is formed within the opening in electrical communication with the at least one electrically conductive feature.

Abstract: There is set forth herein a semiconductor device fabricated on a bulk wafer having a local buried oxide region underneath a channel region of a MOSFET. In one embodiment the local buried oxide region can be self-aligned to a gate, and a source/drain region can be formed in a bulk substrate. A local buried oxide region can be formed in a semiconductor device by implantation of oxygen into a bulk region of the semiconductor device followed by annealing.

Abstract: A semiconductor device includes a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite to the upper surface, a first semiconductor chip having a first main surface, a plurality of first electrodes formed on the first main surface, and a first rear surface opposite to the first main surface, and mounted over the upper surface of the wiring substrate such that the first rear surface of the first semiconductor chip faces the upper surface of the wiring substrate, and a plurality of wires electrically connected with the plurality of terminals, respectively.

Abstract: An organic light emitting display device includes first and second electrodes facing each other on a substrate, a charge generation layer formed between the first and second electrodes, a first light emitting stack formed between the charge generation layer and the first electrode, and a second light emitting stack formed between the charge generation layer and the second electrode, wherein a hole injection layer of a light emitting stack to realize blue color of the first and second light emitting stacks is formed by doping a host formed of hexaazatriphenylene (HAT-CN) with 0.5% to less than 10% of a dopant formed of a hole transporting material based on a volume of the hole injection layer.

Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.

Abstract: A redistribution film for IC package is disclosed, which comprises a top redistribution layer configured on top of a bottom redistribution layer. The top redistribution layer is fabricated following PCB design rule, and the bottom redistribution layer is fabricated following IC design rule. Further, the interface between the top redistribution layer and the bottom redistribution layer is optionally made roughed to increase bonding forces therebetween.

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.

Abstract: The present invention provides a TFT array substrate, the TFT array substrate includes: a first metal layer including a first common electrode line, a second metal layer including a second common electrode line, and a third common electrode line, wherein the third common electrode line is electrically connected with at least one of the first common electrode line and the second common electrode line. The TFT array substrate provided by the present invention can achieve at least one effect of reducing the delay of a common electrode line signal (common signal), reducing flicker inequality and crosstalk without reducing the aperture ratio, lowering the cost and simplifying the manufacturing process.

Abstract: A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate between the lower S/D regions. Raised S/D regions are arranged upon the lower S/D regions adjacent to the RMG structure, respectively. The raised S/D regions may be recessed to form contact trenches. First self-aligned contacts are located upon the raised S/D regions within a first active area and second self-aligned contacts are located upon the recessed raised S/D regions in the second active area. The first and second self-aligned contacts allows for independent reduction of source drain contact resistances. The first self-aligned contacts may be MIS contacts or metal silicide contacts and the second self-aligned contacts may be metal-silicide contacts.

Abstract: Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.

Abstract: A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CDD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CDD.

Abstract: This invention comprises a field effect transistor which comprises source and drain electrodes (01) which are bridged by a semiconductor which comprises semiconducting crystallites, the conductivity of the semiconductor being controlled by a gate electrode (02) which is insulated from the semiconductor and the source and drain electrodes, to which a potential is applied for controlling the conductivity of the semiconductor, in which at least part of the facing surfaces of the source and drain electrodes are geometrically formed such that they provide current flow of different directions between the electrodes through the said channel. By this means current is caused to flow through more orientations of the crystals resulting in greater uniformity of performance between different transistors when there is a degree of variable crystallographic orientation.

Abstract: The semiconductor memory device includes a stacked structure including conductive patterns and interlayer insulating patterns which are alternately stacked, a through-hole configured to pass through the stacked structure; a channel pattern formed inside the through-hole, a first capping conductive pattern formed on the channel pattern, a second capping conductive pattern formed on a sidewall of the first capping conductive pattern and surrounding the first capping conductive pattern, and a contact plug formed on the first capping conductive pattern and the second capping conductive pattern.