Abstract: A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.

Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.

Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having comprising a hole and a conductive layer surrounding the hole, the conductive layer including a first connection point and a second connection point that are located so that a straight line between the first connection point and the second connection point crosses over the hole; an external terminal coupled to the first connection point of the conductive layer of the connection wiring; and an internal circuit coupled to the second connection point of the conductive layer of the connection wiring.

Abstract: A thermal sensor for an aircraft includes a first electrode, a second electrode, a support layer disposed between the first electrode and the second electrode, and a state changing material is configured to disposed within the support layer, wherein the state changing material transitions between a non-conductive state to a conductive state at a threshold temperature to electrically connect the first and second electrodes.

Abstract: In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer, and a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer. The semiconductor die further includes an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is underneath the power rail.

Abstract: A semiconductor device for converting incident light into an electric current includes a semiconductor substrate; an electrode embedded in the semiconductor substrate; an insulation film contacting the electrode in the semiconductor substrate; a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of the first conductivity type, formed sequentially in a depth direction from a side of a front face of the semiconductor substrate; and a fourth semiconductor region of the second conductivity type contacting the insulation film and the second semiconductor region. An impurity concentration of the fourth semiconductor region is greater than an impurity concentration of the second semiconductor region.

Abstract: A resonant body high electron mobility transistor is described with resonance frequencies in gigahertz regime, limited by the cutoff frequency of the readout transistor. Piezoelectric materials form the resonating membrane of the device. Different modes of acoustic resonance, such as a thickness-mode, can be excited and amplified by applying an AC signal to the transducer electrode and proper biasing of all electrodes. The drain electrode reads out the acoustic resonance and amplifies it. The drain electrode is placed at or near where the piezoelectric charge pickup is maximum; whereas, the source electrode is placed at a nodal point with minimum displacement.

Abstract: A Ga—Sb—Ge family of phase change memory materials is described, including GaxSbyGez, wherein a Ga atomic concentration x is within a range from 20% to 45%, a Sb atomic concentration y is within a range from 25% to 40% and a Ge atomic concentration z is within a range from 25% to 55%, is described wherein the material has a crystallization transition temperature Tx greater than 360° C. Adding impurities including one or more element selected from silicon Si, carbon C, oxygen O and nitrogen N, can also increase the crystallization transition temperature Tx to temperatures greater than 400° C., and also reduce reset current.

Abstract: An image sensor includes photodiodes arranged in semiconductor material. Each of the photodiodes is identically sized and is fabricated in the semiconductor material with identical semiconductor processing conditions. The photodiodes are organized into virtual large-small groupings including a first photodiode and a second photodiode. Microlenses are disposed over the semiconductor material with each of microlenses disposed over a respective photodiode. A first microlens is disposed over the first photodiode, and a second microlens is disposed over the second photodiode. A mask is disposed between the first microlens and the first photodiode. The mask includes an opening through which a first portion of incident light directed through the first microlens is directed to the first photodiode. A second portion of the incident light directed through the first microlens is blocked by the mask from reaching the first photodiode. There is no mask between the second microlens and the second photodiode.

Abstract: An organic light emitting display includes a red light emitting layer, a green light emitting layer and a blue light emitting layer formed between first and second electrodes, a hole-transporting layer formed between the first electrode and each of the red, the green and the blue light emitting layers, and an electron-transporting layer formed between the second electrode and each of the red, the green and the blue light emitting layers, wherein at least one light emitting layer of the red, the green and the blue light emitting layers includes a first light emitting layer including a light emitting host and a light emitting dopant, and a second light emitting layer which is formed between the first light emitting layer and at least one of the electron-transporting layer and the hole-transporting layer, and includes the light emitting dopant.

Abstract: A semiconductor light-emitting device comprises a semiconductor stack having a first surface, wherein the first surface comprises multiple protrusion portions and multiple concave portions; a first electrode on the first surface and electrically connecting with the semiconductor stack; a second electrode on the first surface and electrically connecting with the semiconductor stack; and a transparent conduction layer conformally covering the first surface and between the first electrode and the semiconductor stack, wherein the first electrode comprises a first bonding portion and a first extending portion, and the first extending portion is between the first bonding portion and the transparent conduction layer and conformally covers the transparent conduction layer.

Abstract: A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.

Abstract: A method to remove epitaxial semiconductor layers from a substrate by growing an epitaxial sacrificial layer on the substrate where the sacrificial layer is a transition metal nitride (TMN) or a TMN ternary compound, growing one or more epitaxial device layers on the sacrificial layer, and separating the device layers from the substrate by etching the sacrificial layer to completely remove the sacrificial layer without damaging or consuming the substrate or any device layer. Also disclosed are the related semiconductor materials made by this method.

Abstract: A flip-chip light emitting diode chip includes a first semiconductor structure, which includes a P-type semiconductor layer, a N-type semiconductor layer, openings, a reflective layer, a barrier layer, a passivation layer, and an electrical contact layer. The openings penetrate the P-type semiconductor layer and a part of the N-type semiconductor layer so as to partially expose the N-type semiconductor layer. The reflective layer is disposed on the P-type semiconductor layer. The barrier layer is disposed on the reflective layer, and the area of the barrier layer is smaller than that of the reflective layer therefore the reflective layer is exposed from the barrier layer. The passivation layer is disposed on the barrier layer and partially fills in the openings. The electrical contact layer disposed on the passivation layer partially penetrates through the passivation layer to contact the exposed part of the N-type semiconductor layer.

Abstract: A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.

Abstract: A method includes forming at least one fin on a semiconductor substrate. A nanowire material is formed above the fin. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.

Abstract: There are disclosed herein various implementations of composite semiconductor devices including a voltage protected device. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor having a first output capacitance, and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device, the LV device having a second output capacitance. A ratio of the first output capacitance to the second output capacitance is set based on a ratio of a drain voltage of the normally ON III-nitride power transistor to a breakdown voltage of the LV device so as to provide voltage protection for the LV device.

Abstract: One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit, wherein the microelectromechanical layer includes a cap comprising a membrane that extends to the integrated circuit.

Abstract: A package structure of an electronic device is provided. The substrate of such package structure has at least one embedded gas barrier structure, which protects the electronic device mounted thereon and offers good gas barrier capability so as to extend the life of the electronic device.