Abstract: An assembly (101) comprising a semiconductor device (110) with solderable bumps (112); a substrate (120) with a layer (130) of a first insulating compound and an underlying metal layer (140) patterned in contact pads (141) and connecting traces (142), the insulating layer having openings (132) to expose the surface (142a) and sidewalls (142b) of underlying traces; the device bumps soldered onto the contact pads, establishing a gap (150) between device and top insulating layer; and a second insulating compound (160) cohesively filling the gap and the second openings, thereby touching the underlying traces, the second insulating compound having a higher glass transition temperature, a higher modulus, and a lower coefficient of thermal expansion than the first insulating compound.

Abstract: A package design method is disclosed for the optimization of package differential impedance at data rates of 25 Gb/s and beyond. The method optimizes the differential impedance of package vertical interconnections of BGA ball, via, and PTH as well as around the joint between the vertical interconnection and the horizontal interconnection of trace. At 8 ps rise time, a <5% impedance variation is obtained with a 0.8 mm BGA ball pitch and a 10-layer buildup substrate and a <10% impedance variation is obtained with a 1 mm BGA ball pitch and a 14-layer buildup substrate. The method is applicable to all BGA package designs running at 25 Gb/s and beyond.

Abstract: A method of fabricating a semiconductor device, including forming a lower electrode on a substrate; forming a first insulating film covering a periphery of the lower electrode and an upper surface end portion of the lower electrode; forming a second insulating film along an upper surface central portion outside the upper surface end portion of the lower electrode and a side surface and an upper surface of the first insulating film; and forming an upper electrode on the second insulating film.

Abstract: An organic EL element including: an anode and a cathode disposed to face each other with a gap therebetween; a functional layer that contains an organic material and is disposed between the anode and the cathode; and an electron injection layer that has a function to inject electrons into the functional layer and is disposed between the anode and the cathode. The electron injection layer contains a metal oxide with d0 electron configuration, and a Fermi level of the electron injection layer is located in a vicinity of a lower end of a conduction band of the electron injection layer.

Abstract: A TFT array substrate has an organic insulating film formed of a photosensitive organic resin material. A common electrode and a lead-out wiring are formed on the organic insulating film, and a pixel electrode is formed above the common electrode with an interlayer insulating film provided between them. The pixel electrode is connected to the lead-out wiring through a contact hole formed in the interlayer insulating film. The lead-out wiring and the common electrode are connected to a drain electrode and a common wiring, respectively, through contact holes formed in the organic insulating film. A metal cap film is provided on each of the lead-out wiring and the common electrode in the contact holes formed in the organic insulating film.

Abstract: An organic light-emitting display device includes a substrate. A buffer layer is formed on the substrate. A thin film transistor is disposed on the buffer layer. The thin film transistor includes an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer, and a second insulating layer. An uneven pattern is formed by patterning the buffer layer. A first pixel electrode is disposed in an opening formed in the second insulating layer. The first pixel electrode includes a transparent conductive oxide. A second pixel electrode is disposed on the first pixel electrode. The second pixel electrode includes a semi-transmissive layer. An organic lighting-emitting layer is formed on the second pixel electrode. An opposite electrode is formed on the organic lighting-emitting layer.

Abstract: A method for producing a semiconductor element includes a step of forming a multiple quantum well in which a GaSb layer and an InAs layer are alternately stacked on a GaSb substrate by MOVPE, wherein, in the step of forming a multiple quantum well, an InSb film is formed on at least one of a lower-surface side and an upper-surface side of the InAs layer so as to be in contact with the InAs layer.

Abstract: A lateral/vertical device is provided. The device includes a device structure including a device channel having a lateral portion and a vertical portion. The lateral portion of the device channel can be located adjacent to a first surface of the device structure, and one or more contacts and/or a gate can be formed on the first surface. The device structure also includes a set of insulating layers located in the device structure between the lateral portion of the device channel and a second surface of the device structure opposite the first surface. An opening in the set of insulating layers defines a transition region between the lateral portion of the device channel and a vertical portion of the device channel. A contact to the vertical portion of the device channel can be located on the second surface.

Abstract: The invention relates to a module package which comprises a module substrate 1, a chip 2, 3 applied using the flip chip process, and an encapsulation layer 8, and to a method for producing same. The chip 2, 3 has component structures on the top side 13, 14 thereof. Said top said 13, 14 faces the module carrier 1, wherein a gap 4, 5 is formed between the top side 13, 14 of the chip and the module carrier 1. A filler is added to the encapsulation layer 8. The encapsulation layer 8 partly fills underneath the chip 2, 3, wherein at most the part of the chip 2, 3, on which no component structures are present, is underfilled, and at a minimum the material of the encapsulation layer 8 completely encloses the sides of the chip 2, 3.

Abstract: A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate between the lower S/D regions. Raised S/D regions are arranged upon the lower S/D regions adjacent to the RMG structure, respectively. The raised S/D regions may be recessed to form contact trenches. First self-aligned contacts are located upon the raised S/D regions within a first active area and second self-aligned contacts are located upon the recessed raised S/D regions in the second active area. The first and second self-aligned contacts allows for independent reduction of source drain contact resistances. The first self-aligned contacts may be MIS contacts or metal silicide contacts and the second self-aligned contacts may be metal-silicide contacts.

Abstract: Complementary metal-oxide-semiconductor (CMOS) image sensors are provided. A CMOS image sensor includes a substrate including a pixel array and a peripheral circuit region, a photodiode and a floating diffusion region in the pixel array of the substrate, a transfer gate insulating layer and a transfer gate electrode on the substrate between the photodiode and the floating diffusion region, and a peripheral gate insulating layer and a peripheral gate electrode on the peripheral circuit region. The transfer gate electrode includes a first edge that is rounded to have a first radius of curvature, and the peripheral gate electrode includes a second edge that is rounded to have a second radius of curvature smaller than the first radius of curvature.

Abstract: A trench contact epilayer in a semiconductor device is provided. Embodiments include forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions; depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches; removing the SiN layer in the PFET region; growing a germanium (Ge) epilayer over the source/drain regions in the PFET region; depositing metal over the ILD and in the trenches in the NFET and PFET regions; etching the metal in the NFET region to expose the conformal SiN layer; removing the SiN layer in the NFET region; growing a Group III-V epilayer over the source/drain regions in the NFET region; and depositing metal over the ILD and in the trenches in the NFET region.

Abstract: An organic light emitting display device with improved thermal reliability is disclosed. The organic light emitting display device includes a substrate, and an organic light emitting device that includes a first electrode, an organic light emitting layer including a first host, a second host, and a dopant, and a second electrode sequentially stacked on the substrate. The first host and the second host have different glass transition temperatures.

Abstract: A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device.

Abstract: A light emitting element includes: a laminated body including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer in this order, the second conductive semiconductor layer having a light extraction surface; and a recombination suppression structure provided in vicinity of an end surface of the active layer, the recombination suppression structure having a bandgap larger than a bandgap of the active layer.

Abstract: A cap for installing a semiconductor device that can send or receive a light having a predetermined wavelength, the cap including a recess for installing the semiconductor device, the recess being defined by a through-hole penetrating an upper surface of a silicon substrate and a lower surface of the silicon substrate, the through-hole having an upper end part of the through-hole on a side of the upper surface of the silicon substrate and a lower end part of the through-hole on a side of the lower surface of the silicon substrate, and a coating film formed to cover the upper surface of the silicon substrate and the upper end part of the through-hole, wherein the coating film that covers the upper end part of the through-hole is a window part that transmits the light having a predetermined wavelength.

Abstract: A semiconductor device includes: a first semiconductor layer of a nitride semiconductor formed on a substrate; a second semiconductor layer of a nitride semiconductor formed on the first semiconductor layer; and a gate electrode, a source electrode, a drain electrode, and a hole extraction electrode, each of which is formed on the second semiconductor layer, wherein between the source electrode and the hole extraction electrode or in a region right under the source electrode, the first semiconductor layer and the second semiconductor layer form a vertical interface approximately perpendicular to a surface of the substrate, and a surface of the first semiconductor layer configured to form the vertical interface is an N-polar surface.

Abstract: An organic light emitting display device includes first and second electrodes facing each other on a substrate, a charge generation layer formed between the first and second electrodes, a first light emitting stack formed between the charge generation layer and the first electrode, and a second light emitting stack formed between the charge generation layer and the second electrode, wherein a hole injection layer of a light emitting stack to realize blue color of the first and second light emitting stacks is formed by doping a host formed of hexaazatriphenylene (HAT-CN) with 0.5% to less than 10% of a dopant formed of a hole transporting material based on a volume of the hole injection layer.

Abstract: Techniques for processing silicon germanium (SiGe) thin films to reduce surface roughness thereof are provided herein. In an aspect, a method is disclosed that includes depositing a silicon germanium (SiGe) material upon a surface of a substrate at or below about 450 degrees Celsius, the substrate having a plurality of CMOS devices therein and forming, from the deposited SiGe material, a SiGe material film, wherein the SiGe material film has a jagged surface comprising projections and indentations extended along a direction substantially perpendicular to the surface of the substrate. The method further includes performing a chemical mechanical planarization (CMP) process to the jagged surface of the SiGe material, and reducing variations between the projections and the indentions along the direction substantially perpendicular to the surface of the substrate, and transforming the jagged surface of the SiGe material into a relatively smooth surface, compared to the jagged surface.

Abstract: Systems and methods for providing a hybrid integrated nanostructure and nanotube substrate system are disclosed. The system includes a substrate having a plurality of nanostructures formed thereon. Interconnected to the substrate, directly or through nanostructures, are nanotubes. The nanostructures can extend for a greater distance from the surface of the substrate than the nanotubes, providing a robust structure. In addition, the structure can be highly emissive and absorptive hybrid surface.