Abstract: A semiconductor device includes a first fin feature embedded within an isolation structure disposed over a semiconductor substrate, the first fin structure having a first sidewall and a second opposing sidewall and a top surface extending from the first sidewall to the second sidewall. The device also includes a second fin feature disposed over the isolation structure and having a third sidewall and a fourth sidewall. The third sidewall is aligned with the first sidewall of the first fin structure. The device also includes a gate dielectric layer disposed directly on the top surface of the first fin structure, the third sidewall and the fourth sidewall of the second fin feature and a gate electrode disposed over the gate dielectric.

Abstract: A semiconductor device according to an embodiment, includes a plurality of wires, a first dielectric film, and a second dielectric film. The plurality of wires are arranged above a semiconductor substrate so as to extend in a first direction and aligned via a first cavity. The first dielectric film has a plurality of portions arranged above the plurality of wires so as to extend in a second direction substantially perpendicular to the plurality of wires and aligned along the first direction via a second cavity leading to the first cavity. The second dielectric film is formed above the first dielectric film so as to cover the second cavity.

Abstract: The present invention aims to control power consumption of a light emitting display device by reducing parasitic capacitance between wires in a drive circuit part of a periphery region. The light emitting display device of the present invention includes an insulation film arranged above a substrate, a first wiring arranged above the insulation film in a pixel region, a second wiring arranged above the insulation film in a periphery region of a periphery of the pixel region, a common electrode continuously arranged to the pixel region and the periphery region, a first insulation layer arranged between the first wiring and the common electrode, and a second insulation layer arranged between the second wiring and the common electrode and having a larger thickness than the first insulation layer.

Abstract: A light emitting element includes a semiconductor including an active layer, and a planar shape of the light emitting elements including a concave polygon. The planar shape of the concave polygon has interior angles including at least one acute angle.

Abstract: A drain extended metal oxide semiconductor (MOS) includes a substrate having a semiconductor. A gate is located on the semiconductor, a source is located on the semiconductor and on one side of the gate, and a drain is located on the semiconductor and on another side of said gate. The MOS includes least one first finger having a first finger drain component located adjacent the drain, the first finger drain component has a silicide layer. At least one second finger has a second finger drain component located adjacent the drain, the second finger drain component has less silicide than the first finger drain component.

Abstract: The aim is to improve the bending resistance a display device. The display device in one embodiment includes a substrate including a first surface and a second surface and a curved part between the first surface and the second surface, a display element arranged on the first surface, a conducting layer connected with the display element and extending to the second surface from the first surface via the curved part, a plurality of protective layers having a lower ductility than the substrate and arranged in the substrate side and/or opposite side to the substrate side with respect to the conducting layer and along the curved part, wherein each of the plurality of protective layers spreading over the curved part, to a certain region of the first surface side from the curved part, and to a certain region of the second side from the curved part.

Abstract: The present invention discloses a high density film for IC package. The process comprises: a redistribution layer is fabricated following IC design rule, with a plurality of bottom pad formed on bottom, and with a plurality of first top pad formed on top; wherein the density of the plurality of bottom pad is higher than the density of the plurality of first top pad; and a top redistribution layer is fabricated following PCB design rule, using the plurality of the first top pad as a starting point; with a plurality of second top pad formed on top; wherein a density of the plurality of first top pad is higher than a density of the plurality of second top pad.

Abstract: A liquid crystal display device is disclosed. The liquid crystal display device includes a first substrate, a second substrate opposite of the first substrate, and a TFT layer on the first substrate. The TFT layer includes a gate electrode metal layer, and a source/drain electrode metal layer, where the source/drain electrode metal layer overlaps the gate electrode metal layer. The display device also includes an alignment film layer on a side of the first substrate that faces the second substrate, and on a side of the second substrate that faces the first substrate. The display device also includes at least one protrusion on at least a part of a side of at least one of the gate electrode metal layer and the source/drain electrode metal layer that faces the first substrate, where the protrusion is configured to reflect incident light from a side of the first substrate.

Abstract: A semiconductor device includes a third first-conductivity-type semiconductor layer on a semiconductor substrate; a first pillar-shaped semiconductor layer formed on the semiconductor substrate and including a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, a second second-conductivity-type semiconductor layer, and a third second-conductivity-type semiconductor layer; a first gate insulating film around the first body region; a first gate around the first gate insulating film; a second gate insulating film around the second body region; a second gate around the second gate insulating film; an output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer; and a first contact that connects the first gate and the second gate.

Abstract: An optical interconnect is located on a surface of a semiconductor handle substrate. The optical interconnect includes a waveguide core material portion that is completely surrounded on all four sides by a dielectric oxide-containing cladding structure. The dielectric oxide-containing material of the dielectric oxide-containing cladding structure that is located laterally adjacent end segments of the waveguide core material portion is configured to include a sidewall surface that can receive and transmit light. A plurality of semiconductor devices can be formed above the topmost dielectric oxide-containing material of the dielectric oxide-containing cladding structure.

Abstract: Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a substrate, the first semiconductor region having a first conductivity type; and a second semiconductor region disposed at least partially within the first semiconductor region, the second semiconductor region having a second conductivity type, wherein the first semiconductor region separates the second semiconductor region from the substrate. In one embodiment, the substrate and the first semiconductor region have a sigma-shaped boundary. In another embodiment, the substrate and the first semiconductor region have U-shaped boundary.

Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

Abstract: A redistribution film for IC package is disclosed, which comprises a top redistribution layer configured on top of a bottom redistribution layer. The top redistribution layer is fabricated following PCB design rule, and the bottom redistribution layer is fabricated following IC design rule. Further, the interface between the top redistribution layer and the bottom redistribution layer is optionally made roughed to increase bonding forces therebetween.

Abstract: An electronic circuit unit includes a circuit substrate having a rectangular shape and is obtained by cutting an integral substrate along a vertical cut line and a horizontal cut line to be separated; a copper foil land soldered to components; and a substrate outer edge, which is formed by cutting, of two sides orthogonal to each other. The copper foil land and the substrate outer edge are positioned in the vicinity of a corner of the circuit substrate. Solder resist is provided around the copper foil land. A plurality of substrate exposure portions without the solder resist is provided in the vicinity of the substrate outer edge.

Abstract: A high-electron-mobility field effect transistor is formed with a buffer region having a stepped lateral profile, the stepped lateral profile having first, second and third cross-sections of the buffer region, the first cross-section being thicker than the third cross-section and including a buried field plate, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections. A barrier region is formed along the stepped lateral profile. The barrier region is separated from the buried field plate by a portion of the buffer region. The buffer region is formed from a first semiconductor material and the barrier region is formed from a second semiconductor material. The first and second semiconductor materials have different band-gaps such that an electrically conductive channel of a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions.

Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

Abstract: Silicon-on-insulator integrated circuits including body contact structures and methods for fabricating the same are disclosed. A method for fabricating a silicon-on-insulator integrated circuit includes filling a plurality of first and second shallow isolation trenches with an insulating material to form plurality of first and second shallow trench isolation (STI) structures, the plurality of second shallow isolation trenches having doped regions therebeneath, and forming a gate structure over the semiconductor layer that includes a first portion disposed over and parallel to at least two of the plurality of second STI structures and a second portion disposed in between the at least two of the plurality of second STI structures. The method further includes forming contact plugs to a body contact or gate region of the semiconductor layer.

Abstract: Sensor device packages and related fabrication methods are provided. An exemplary sensor device package includes a first structure having a sensing arrangement thereon, a second structure having circuitry thereon, and a conductive structure within the first structure and coupled to the circuitry to provide an electrical connection to the circuitry through the first structure. Thus, circuitry on the second structure may be electrically connected to an interface of the sensor device package through the first structure.

Abstract: Disclosed is a light emitting device comprising a plurality of light emitting cells, and a bridge electrode electrically connecting two adjacent light emitting cells, and the plurality of light emitting cells comprise a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer between the first conductive semiconductor layer and the second conductive semiconductor layer, a first electrode on the first conductive semiconductor layer and a second electrode on the second conductive semiconductor layer, wherein the bridge electrode has a part thicker than the first electrode and the second electrode.