Abstract: An electronic device, such as a thin-film transistor, includes a substrate and a dielectric layer formed from a dielectric composition. The dielectric composition includes a dielectric material, a crosslinking agent, and an infrared absorbing agent. In particular embodiments, the dielectric material comprises a lower-k dielectric material and a higher-k dielectric polymer. When deposited, the lower-k dielectric material and the higher-k dielectric material form separate phases. The infrared absorbing agent allows the dielectric composition to attain a temperature that is significantly greater than the temperature attained by the substrate during curing. This difference in temperature allows the dielectric layer to be cured at relatively high temperatures and/or shorter time periods, permitting the selection of lower-cost substrate materials that would otherwise be deformed by the curing of the dielectric layer.

Abstract: An ultraviolet sensor has a p-type semiconductor layer composed of a solid solution of NiO and ZnO, and an n-type semiconductor layer composed of ZnO and joined to the p-type semiconductor layer such that a part of the surface of the p-type semiconductor layer is exposed. In the p-type semiconductor layer, trivalent Ni is contained in a crystal grain in a state of being solid-solved with the solid solution of NiO and ZnO. The trivalent Ni can be contained in the crystal grain of the p-type semiconductor layer by adding NiOOH to NiO and ZnO, and firing the resulting mixture. Thereby, an inexpensive ultraviolet sensor capable of being downsized, which can easily detect the intensity of ultraviolet light by a photovoltaic power without utilizing a peripheral circuit can be realized.

Abstract: An electronic component has a housing body which comprises a semiconductor chip in a recess. The semiconductor chip in the recess is embedded in a casting compound made of a first plastic material having a first glass transition temperature. A cover element made of a second plastic material having a second glass transition temperature is arranged above the recess. The second glass transition temperature is lower than the first glass transition temperature.

Abstract: A gallium nitride-based group III-V compound semiconductor light emitting device and a method for fabricating the same are provided. The gallium nitride-based group III-V compound semiconductor light emitting device includes: a substrate; a p-type ohmic electrode layer formed on the substrate; a p-type gallium nitride-based group III-V compound semiconductor layer formed on the p-type ohmic electrode layer; an n-type gallium nitride-based group III-V compound semiconductor layer formed on the p-type gallium nitride-based group III-V compound semiconductor layer; an n-type ohmic electrode layer formed on the n-type gallium nitride-based group III-V compound semiconductor layer; and first and second refractive index adjustment layers having refractive index smaller than those of the n-type gallium nitride-based group III-V compound semiconductor layer and the n-type ohmic electrode layer, wherein a pyramid structure is formed on the surface of the second refractive index adjustment layer.

Abstract: Disclosed herein is a device that includes a semiconductor substrate having a first area, a plurality of cell transistors arranged on the first area of the semiconductor substrate, and a plurality of cell capacitors each coupled to an associated one of the cell transistors, the cell capacitors being provided so as to overlap with one another on the first area.

Abstract: Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a plurality of lamination units being continuously laminated. The lamination unit includes: a composition modulation layer formed of a first and a second unit layer having different compositions being alternately and repeatedly laminated such that a compressive strain exists therein; a termination layer formed on an uppermost portion of the composition modulation layer, the termination layer acting to maintain the compressive strain existing in the composition modulation layer; and a strain reinforcing layer formed on the termination layer, the strain reinforcing layer acting to enhance the compressive strain existing in the composition modulation layer.

Abstract: A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness. The support element can have a body of at least one of dielectric or semiconductor material exposed at a second surface of the support element, openings extending through a thickness of the body, conductive vias extending within at least some of the openings in a direction of the thickness of the body, and terminals exposed at a first surface of the support element. The second surface of the support element can be united with the second surface of the substrate element. The terminals can be electrically connected with the contacts through the conductive vias and the electrically conductive structure.

Abstract: In one surface of a semiconductor substrate, an n? layer, a p base layer, a p well layer, another p well layer, a channel stopper layer, an emitter electrode, a guard ring electrode, and a channel stopper electrode for example are formed. In the other surface of the semiconductor substrate, an n+ buffer layer, a p+ collector layer, and a collector electrode are formed. In a curved corner of the p well layer, a p low-concentration layer having a lower impurity concentration than the impurity concentration of the p well layer is formed from the surface to a predetermined depth.

Abstract: According to one embodiment, a display device includes a substrate, a thin film transistor, a passivation film, a hydrogen barrier film, a pixel electrode, an organic light emitting layer, an opposite electrode, and a sealing film. The thin film transistor is provided on a major surface of the substrate. The thin film transistor includes a gate electrode, a gate insulating film, a semiconductor film, a first conducting portion, and a second conducting portion. The passivation film is provided on the thin film transistor. The hydrogen barrier film is provided on the passivation film. The pixel electrode is electrically connected to one of the first conducting portion and the second conducting portion. The organic light emitting layer is provided on the pixel electrode. The opposite electrode is provided on the organic light emitting layer. The sealing film is provided on the hydrogen barrier film and the opposite electrode.

Abstract: Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.

Abstract: A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV. A metal based contact is formed in the contact region. The metal based contact has a depth DC which is equal to about DV. The vacancy defects lower the resistance of the metal based contact with the substrate.

Abstract: Disclosed is a semiconductor device including: an active region defined by an element isolation region; a gate trench going across the active region to define source/drain regions on both sides thereof, respectively, and to define, between the source/drain regions, the channel region having a first, second, and third protruding portions which are arranged in a gate width direction; and a gate electrode formed in the gate trench so as to cover the channel region through a gate insulating film.

Abstract: A semiconductor device and manufacturing method therefor includes a ?-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a ?-shaped recess.

Abstract: A semiconductor device has a first MIS transistor. The first MIS transistor includes a first source/drain region of a first conductivity type which includes a silicon compound layer causing a first stress in a gate length direction of a channel region in a first active region, and a stress insulating film which is formed on the first active region to cover a first gate electrode, a first sidewall, and the first source/drain region, and which causes a second stress opposite to the first stress. An uppermost surface of the silicon compound layer is located higher than a surface of a semiconductor substrate located directly under the first gate electrode. A first stress-relief film is formed in a space between the silicon compound layer and the first sidewall.

Abstract: Power supply plugs, which couple a power supply active region to a power supply metal interconnect, include a plurality of first plugs, which are arranged at first pitches of a predetermined length, and a second plug, which is spaced apart from the closest one of the first plugs by a center-to-center distance different from an integral multiple of the predetermined length. Among the power supply plugs, the second plug is closest to a third plug, which is an interconnect plug closest to the power supply active region and the power supply metal interconnect.

Abstract: A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode.

Abstract: A thyristor includes a base region, a pair of first doping regions, at least one second doping region, at least one third doping region, and a pair of metal layers. The first doping regions are formed in two opposite sides of the base region and touch the base region. The second doping region is formed between the base region and one of the first doping regions. The second doping region touches the base region and the first doping region. The third doping region is formed in one of the first doping regions and touches the first doping region. The type of the first doping region is different from the types of the second doping region, the third doping region, and the base region. The metal layers touch the first doping regions respectively. The first doping regions and the third doping region are located between the metal layers.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; a plurality of semiconductor regions; second semiconductor region; a first electrode being positioned between the plurality of first semiconductor regions, the first electrode contacting with the semiconductor layer, each of the plurality of first semiconductor regions, and the second semiconductor region via a first insulating film; a second electrode provided below the first electrode, and contacting with the semiconductor layer via a second insulating film; an insulating layer interposed between the first electrode and the second electrode; a third electrode electrically connected to the semiconductor layer; and a fourth electrode connected to the second semiconductor region. The first electrode has a first portion and a pair of second portions. And each of the pair of second portions is provided along the first insulating film.

Abstract: A first dual-gate electrode includes a gate electrode located on a first active region and having a first silicon film of a first conductivity type and a gate electrode located on a second active region and having a first silicon film of a second conductivity type. A second dual-gate electrode includes a gate electrode located on a third active region and having a second silicon film of the first conductivity type and a gate electrode located on a fourth active region and having a second silicon film of the second conductivity type. At least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.

Abstract: A device manufacturing method including substrate preparation, pixel electrode formation, photosensitive film formation, first part exposure, second part exposure, and development. In first part exposure, after execution of photosensitive film formation, first photomask is arranged to face substrate and exposure is performed to cause first part of photosensitive film to be exposed to light via first photomask. In second part exposure, after or together with execution of first part exposure, second photomask is arranged to face substrate and exposure is performed to cause second part of photosensitive film, which is different from first part at least partially, to be exposed to light via second photomask. In second part exposure, second photomask is arranged such that end thereof overlaps with end of first photomask, and overlap between first and second photomasks positionally corresponds to electrical wire.