Abstract: An array substrate, a method for fabricating the same and a display device as provided relate to the field of display technologies and can overcome the disadvantage of the gate-source capacitance being inconstant and prevent screen flicker, thereby improving the display effect of the display device. The array substrate comprises a plurality of pixel units (31) arranged into an array and a gate line (32) and a data line (33) disposed as intersecting each other and corresponding to each of the pixel units (31), each of the pixel units comprising a TFT region (311) and a pixel electrode region (312), the TFT region (311) comprises at least two TFTs (34, 35); a source electrode (341, 351) of each of the TFTs is electrically connected to the data line (33), a gate electrode (342, 352) of each of the TFTs is electrically connected to the gate line (32), a drain electrode (343, 353) of each of the TFTs is electrically connected to a pixel electrode (312).

Abstract: A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.

Abstract: An OLED display panel is provided which can dissipate heat generated from a circuit on the OLED display panel to the exterior using a structure which can rapidly reduce costs. A metal film 2 and insulation film 3 are formed between a glass substrate 1 and TFT drive circuit layer 4 in sequence from the side of the glass substrate 1. The metal film 2 conducts with a heat dissipation pattern 5b formed above the TFT drive circuit layer 4 from the metal film via a contact 15 which passes through the insulation film 3 and TFT drive circuit layer 4. The heat dissipation pattern 5b is connected to a metal frame 20 via a heat dissipation tape 21.

Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.

Abstract: There is a need to provide a semiconductor device and an electronic device capable of easily allowing a bypass capacitor to always improve noise suppression on a signal path in order to transmit a reference potential between chips in different power supply noise states. There is provided a specified signal path that connects a control chip and a memory chip mounted on a mounting substrate and transmits a reference potential generated from the control chip. A bypass capacitor is connected to the specified signal path only at a connecting part where a distance from a reference potential pad of the memory chip to the connecting part along the specified signal path is shorter than a distance from a reference potential pad of the control chip to the connecting part along the specified signal path.

Abstract: Provided are a light receiving element etc. which have a high responsivity over the near- to mid-infrared region and stably have a high quality while maintaining the economical efficiency. The light receiving element includes an InP substrate that is transparent to light having a wavelength of 3 to 12 ?m, a middle layer that is epitaxially grown on the InP substrate, a GaSb buffer layer located in contact with the middle layer, and a light-receiving layer that is epitaxially grown on the GaSb buffer layer and that has a type-II multiple quantum well structure. The GaSb buffer layer is epitaxially grown on the middle layer while exceeding a range of a normal lattice-matching condition.

Abstract: An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.

Abstract: An organic light emitting diode device includes an array substrate including a display region where a plurality of pixel regions each include a light emitting diode, and a non-display region surrounding the display region; and a protection layer covering the display region, extending to the non-display region, and including a round corner, wherein a maximum of a radius of the corner of the protection layer is determined according to a distance between a side of the protection layer and a side of the display region corresponding to the side of the protection layer, and the radius of the corner is at least 0.1 mm.

Abstract: An integrated circuit device having improved radiation immunity is described. The integrated circuit device comprises an n-type wafer having a first surface and a second surface; a p-type epitaxial layer formed on the first surface of the n-type wafer, the p-type epitaxial wafer having first elements storing charge; and an n-well formed in the p-type epitaxial layer, the n-well having second elements storing charge; wherein the n-type wafer is positively biased to attract excess minority carriers in the p-type epitaxial layer. A method of improving radiation immunity in an integrated circuit is also described.

Abstract: In a coating-type electron injection layer or electron transport layer using a metal oxide, the present invention aims at improving uniformity or stability of composition distribution and adhesion with another adjoining constituent layer, and improving film forming property, to thereby provide an organic electronic device and manufacture of the device whose efficiency is improved. In the organic electronic device having one pair of electrodes on a substrate, and having at least one organic layer between the electrodes, the electron injection layer or the electron transport layer is formed by application of a liquid material in which an alkaline metal salt and zinc-oxide nano particles are dissolved in alcohol.

Abstract: An organic light-emitting diode (OLED) display according to an exemplary embodiment of the present invention includes a substrate, a thin film transistor formed on the substrate, a pixel electrode formed on the thin film transistor and electrically connected to the thin film transistor, a pixel definition layer formed on the pixel electrode so as to define a pixel region, an emission layer formed on the pixel electrode and contacting the pixel electrode in the pixel region, and an interlayer formed on the pixel definition layer and contacting part of the emission layer. One side of the interlayer has an uneven shape so that a surface area of the interlayer is increased.

Abstract: To provide a highly reliable light-emitting device and especially a light-emitting device which can be formed without use of a metal mask and includes a plurality of light-emitting elements. A structural body at least an end of which has an acute-angled shape is provided so that the end can pass downward through an electrically conductive film formed over the insulating layer and can be at least in contact with an insulating layer having elasticity, thereby physically separating the electrically conductive film, and the electrically conductive films are thus electrically insulated from each other. Such a structure may be provided between adjacent light-emitting elements so that the light-emitting elements can be electrically insulated from each other in the light-emitting device.

Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.

Abstract: A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (Pt)-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.

Abstract: A light-emitting device includes a first light-emitting element disposed on a substrate, a convex-shaped first sealing resin that includes an annular portion formed in a closed annular shape in a top view and seals the first light-emitting element, a second light-emitting element disposed on the substrate in a region surrounded by the annular portion of the first sealing resin, and a second sealing resin filled in the region surrounded by the annular portion so as to seal the second light-emitting element. One of the first and second sealing resin includes a phosphor particle or the first and second sealing resins include a phosphor particle to emit a different fluorescent color from each other.

Abstract: A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.

Abstract: Provided is an organic light-emitting display device for forming a strong sealing structure. The organic light-emitting display device includes: a lower electrode that is disposed on a substrate; a first barrier wall that protrudes beyond a top surface of the lower electrode; and a second barrier wall that is disposed on at least a top surface of the first barrier wall and has a cross-section having a reverse-tapered shape, wherein the second barrier wall includes a low temperature viscosity transition (LVT) inorganic material including tin oxide.

Abstract: The objects of the present invention are to provide an organic luminescent material capable of being easily controlled for dopant concentrations. The present invention is characterized in that a organic light-emitting device comprising a upper electrode, a lower electrode; and a light-emitting layer positioned between the upper electrode and the lower electrode, wherein the light-emitting layer contains a host, a first dopant and a second dopant, the first dopant is a blue-light-emitting dopant or a green-light-emitting dopant, the first dopant has a first functional group, and the first functional group makes the first dopant transfer toward the surface of the light-emitting layer on the upper electrode side in the light-emitting layer.

Abstract: To enhance the reliability of a semiconductor device. The semiconductor device includes a wiring substrate having a plurality of bonding fingers (terminal) formed on a chip-mounting surface, a semiconductor chip mounted on the wiring substrate, a plurality of wires having a ball part and a stitch part respectively. The bonding fingers have a first bonding finger to which the stitch part of the first wire is coupled respectively, and the second bonding finger to which a ball part of the second wire is coupled. In addition, in plan view, the second bonding finger is arranged at a position different from the arrangement of a plurality of first bonding fingers, and the width of the second bonding finger is larger than the width of the first bonding finger.

Abstract: A method of producing an optoelectronic semiconductor component includes arranging a semiconductor layer stack with a pn-junction on a substrate, lateral patterning of the semiconductor layer sack into a plurality of pairs of first semiconductor bodies and second semiconductor bodies spaced from one another in a lateral direction, detaching the substrate from the pairs of first semiconductor bodies and second semiconductor bodies, applying at least one pair of first semiconductor bodies and second semiconductor bodies to a connection carrier including electrical connection points and/or at least one conductor track, and electrically connecting the semiconductor bodies of a pair of first semiconductor bodies and second semiconductor bodies by the connection points and/or the at least one conductor track such that the pn-junction of the first semiconductor body connects in antiparallel to the pn-junction of the second semiconductor body.