Abstract: A method and system are provided for a molded electronic package geometry that enables control of warpage and die stress. A mold tool can be closed to define a space or cavity about a semiconductor die disposed on a substrate. Once the mold tool is closed, a mold material can be applied to the space to produce a mold cap. The mold cap geometry can have a first surface that is in contact with the surface of the substrate and a second surface that is opposite the first surface. The second surface can define a tapered portion of the mold cap in which the larger thickness of the tapered portion of the mold cap is in proximity to the semiconductor die and the smaller thickness of the tapered portion of the mold cap is away from the semiconductor die. The thickness of the tapered portion can vary linearly or non-linearly.

Abstract: An organic electroluminescent display device of the invention includes an element substrate, an organic electroluminescent light-emitting element disposed on the element substrate, and a sealing film disposed on the organic electroluminescent light-emitting element, wherein the organic electroluminescent light-emitting element includes an anode formed of metal and disposed on the element substrate, a light-emitting layer disposed on the anode, and a transparent cathode disposed on the light-emitting layer, and the sealing film includes a light-transmittance-reducing layer colored in black.

Abstract: A wiring substrate includes a substrate, a first insulating layer formed on the substrate, wiring patterns formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer. The second insulating layer covers the wiring patterns and includes a first opening that partially exposes adjacent wiring patterns as a pad. A projection is formed in an outer portion of the substrate located outward from where the first opening is arranged. The projection rises in a thickness direction of the substrate.

Abstract: A substrate-through electrical connection (10) for connecting components on opposite sides of a substrate, and a method for making same. The connection includes a substrate-through via made from substrate material (10?). There is a trench (11) provided surrounding the via, the walls of the trench being coated with a layer of insulating material (12) and the trench (11) is filled with conductive or semi-conductive material (13). A doping region (15) for threshold voltage adjustment is provided in the via material in the surface of the inner trench wall between insulating material (12) and the material (10?) in the via. There are contacts (17?, 17?) to the via on opposite sides of the substrate, and a contact (18) to the conductive material (13) in the trench (11) so as to enable the application of a voltage to the conductive material (13).

Abstract: An apparatus includes a flip-chip semiconductor substrate, a light detection element configured to be formed over the flip-chip semiconductor substrate and to have a laminate structure including a first semiconductor layer of a first-conductive-type, a light-absorption layer formed over the first semiconductor layer, and a second semiconductor layer of a second-conductive-type formed over the light-absorption layer, an inductor configured to be connected to the light detection element over the flip-chip semiconductor substrate, an output electrode for bump connection configured to output a current generated by the light detection element through the inductor, a bias electrode for bump connection configured to apply a bias voltage to the light detection element through a bias electrode, and a line configured to cause a metal line of the inductor and the light detection element to be connected to the output electrode or the bias electrode.

Abstract: Provided is an image sensor including a semiconductor substrate having a trench and having a first conductivity type, a photoelectric conversion layer formed in the semiconductor substrate below the trench to have a second conductivity type, first and second transfer gate electrodes provided in the trench covered with a gate insulating layer, a first charge-detection layer formed in the semiconductor substrate adjacent to the first transfer gate electrode, and a second charge-detection layer formed in the semiconductor substrate adjacent to the second transfer gate electrode.

Abstract: A method and an electronic component including: a substrate including at least a hole at least partially going through a thickness of the substrate; an electrically conducting element positioned in the hole and configured to form an electric connection through the hole, wherein the electrically conducting element includes an electrically conducting and self-supporting pillar with a height oriented according to the thickness of the substrate; and a space between at least a part of the wall of the hole and a part of a peripheral wall of the pillar.

Abstract: An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SixBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is carbon-containing silicon nitride formed using a hydrocarbon reagent. A second layer of the hard mask is chlorine-containing silicon nitride formed on the first layer using a chlorinated silane reagent. After SiGe epitaxial source/drain regions are formed, the hard mask is removed using a wet etch which removes the second layer at a rate at least three times faster than the first layer.

Abstract: A white organic light emitting device includes: first and second electrodes formed to face each other on a substrate; a first stack configured with a hole injection layer, a first hole transportation layer, a first light emission layer and a first electron transportation layer which are stacked between the first and second electrodes; a second stack configured with a second hole transportation layer, a second light emission layer, a third light emission layer, a second electron transportation layer and an electron injection layer which are stacked between the first stack and the second electrode; and a charge generation layer interposed between the first and second stacks and configured to adjust a charge balance between the two stacks.

Abstract: A three-dimensional integrateds circuit structure includes a first metal circuit substrate, an interposer substrate disposed on the first metal circuit substrate and electrically connected therewith, and at least one semiconductor component disposed on the interposer substrate. The interposer substrate is used to dissipate the heat generated by the operation of the semiconductor components, so as to achieve the objective of increasing the lifespan of the semiconductor components.

Abstract: A semiconductor device and a method of manufacturing the device is disclosed. In one aspect, a method includes providing a substrate, providing a first epitaxial semiconducting layer on top of the substrate, and forming a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50.

Abstract: A light emitting device includes a first semiconductor layer having a first conductive dopant, an active layer on the first semiconductor layer, an electron blocking layer on the active layer, a carrier injection layer between the active layer and the electron blocking layer, and a second semiconductor layer having a second conductive dopant on the electron blocking layer. The carrier injection layer includes the first conductive dopant and the second conductive dopant, and the first conductive dopant of the carrier injection layer has a concentration lower than a concentration of the second conductive dopant.

Abstract: A transistor which includes an electron transit layer and an electron supply layer which are stacked in a thickness direction of a substrate; an electron transit layer formed over the substrate in parallel to the electron transit layer and the electron supply layer; an anode electrode which forms a Schottky junction with the electron transit layer; and a cathode electrode which forms an ohmic junction with the electron transit layer are provided. The anode electrode is connected to a source of the transistor, and the cathode electrode is connected to a drain of the transistor.

Abstract: An optoelectronic semiconductor component includes a carrier which has an upper side and a lower side opposite to the upper side. At least one radiation-emitting semiconductor device is disposed on the upper side and has a radiation emission surface, through which at least a portion of the electromagnetic radiation, which is generated during operation of the semiconductor device, leaves the semiconductor device. A radiation-absorbing layer is arranged to absorb ambient light, which impinges upon the component, such that an outer surface of the component facing away from the carrier appears black at least in places.

Abstract: Various embodiments provide electrostatic discharge protection structures and methods for forming the same. An exemplary structure can include a semiconductor chip including a through hole. The structure can further include a through silicon via (TSV) structure disposed within the through hole and passing through the semiconductor chip. The TSV structure can have a first surface and a second surface. The structure can further include a tunneling dielectric layer disposed on the first surface of the TSV structure. The tunneling dielectric layer can have a surface area covering a top view surface area of the TSV structure and a surface portion of the semiconductor chip surrounding the TSV structure. Yet further, the structure can include a metal material discretely dispersed in the tunneling dielectric layer, a first electrode disposed on the tunneling dielectric layer, and a second electrode disposed on the second surface of the TSV structure.

Abstract: A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.

Abstract: A method for forming a multi-level stack having a multi-level contact is provided. The method includes forming a multi-level stack comprising a specified number, n, of conductive layers and at least n?1 insulating layers. A via formation layer is formed over the stack. A first via is etched in the via formation layer at a first edge of the stack. A first multi-level contact is formed in the first via. For a particular embodiment, a second via may be etched in the via formation layer at a second edge of the stack and a second multi-level contact may be formed in the second via.

Abstract: A method of producing an optoelectronic semiconductor component includes providing a carrier having a top side, an underside situated opposite the top side, and a plurality of connection areas arranged at the top side alongside one another in a lateral direction; applying a plurality of optoelectronic components arranged at a distance from one another in a lateral direction at the top side, the components having a contact area facing away from the carrier; applying protective elements to the contact and connection areas; applying an electrically insulating layer to exposed locations of the carrier, contact areas and protective elements; producing openings in the insulating layer by removing protective elements; and arranging an electrically conductive material on the insulating layer and in the openings, wherein the electrically conductive material connects a contact area to an assigned connection area.

Abstract: A semiconductor device using a high-k dielectric film is provided. The semiconductor device comprises a first gate insulating layer on a substrate and a first barrier layer on the first gate insulating layer, the first barrier layer having a first thickness. A first work function control layer is on the first barrier layer. A second barrier layer is present on the first work function control layer, the second barrier layer having a second thickness that is less than the first thickness.