Patents Examined by Lawrence Tynes, Jr.
  • Patent number: 10174226
    Abstract: An adhesive composition comprising silver particles containing silver atoms and zinc particles containing metallic zinc, wherein the silver atom content is 90 mass % or greater and the zinc atom content is from 0.01 mass % to 0.6 mass %, with respect to the total transition metal atoms in the solid portion of the adhesive composition.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: January 8, 2019
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Hideo Nakako, Toshiaki Tanaka, Michiko Natori, Dai Ishikawa, Hiroshi Matsumoto
  • Patent number: 10153306
    Abstract: A radio-frequency (RF) device includes a semiconductor substrate, a first field-effect transistor (FET) disposed on the substrate, the first FET having a first plurality of drain fingers, and a second FET connected in series with the first FET along a first dimension, the second FET having a second plurality of drain fingers that extent in a second dimension that is orthogonal with respect to the first dimension.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: December 11, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Tzung-Yin Lee, Aniruddha B. Joshi, David Scott Whitefield, Maureen Rosenberg Brongo
  • Patent number: 10128266
    Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Hoon Lee, Keejeong Rho, Sejun Park, Jinhyun Shin, Dong-Sik Lee, Woong-Seop Lee
  • Patent number: 10109630
    Abstract: The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tian Choy Gan, Chu-Yun Hsiao, Chia-Fu Hsu
  • Patent number: 10103221
    Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: October 16, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: In Su Kim, Jeong Hwan Park, Seung Sik Park, Ha Yong Yang
  • Patent number: 10096628
    Abstract: Provided is a novel semiconductor device. A switching element, specifically a transistor having a well potential structure is manufactured by utilizing a structure including at least a composite material in which a first region and a second region are stacked over a base like a superlattice. The thickness of each of the first region and the second region is greater than or equal to 0.5 nm and less than or equal to 5 nm. A band structure can be controlled by adjusting the number of stacks, which enables application to a variety of semiconductor elements.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10096497
    Abstract: A substrate liquid processing apparatus includes a liquid processing unit configured to process a substrate by a processing liquid, and a controller. The controller processes the substrate in the liquid processing unit, and switches the processing liquid discharged from a discharge line, from a recycling line, to a waste line in which the processing liquid is discarded through the discharge line to the outside, according to a concentration of an elution component eluted from the substrate.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 9, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Hideaki Sato
  • Patent number: 10096556
    Abstract: A semiconductor device includes a substrate and a conductive layer. The substrate has an upper surface that is a substantially rectangular shape having a pair of two sides extending in a first direction and a pair of two sides extending in a second direction. The conductive layer is provided on the substrate and extending along a periphery of the substrate. The conductive layer extends and zigzags toward the first direction.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takayuki Kumai
  • Patent number: 10090329
    Abstract: A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support substrate supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate. A transistor element is formed in the element region, the transistor element having a transistor buried impurity layer formed within the active layer. The semiconductor device further includes a substrate contact having a contact buried impurity layer formed within the contact region and a through contact extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer, the contact buried impurity layer being in the same layer as the transistor buried impurity layer.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 2, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Hiroshi Kumano
  • Patent number: 10083864
    Abstract: A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Patent number: 10068988
    Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
  • Patent number: 10062608
    Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: August 28, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, James M. Wark, William Mark Hiatt
  • Patent number: 10062563
    Abstract: Methods and apparatuses for depositing films in high aspect ratio features and trenches using a post-dose treatment operation during atomic layer deposition are provided. Post-dose treatment operations are performed after adsorbing precursors onto the substrate to remove adsorbed precursors at the tops of features prior to converting the adsorbed precursors to a silicon-containing film. Post-dose treatments include exposure to non-oxidizing gas, exposure to non-oxidizing plasma, and exposure to ultraviolet radiation.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 28, 2018
    Assignee: Lam Research Corporation
    Inventors: Purushottam Kumar, Adrien LaVoie, Ishtak Karim, Jun Qian, Frank L. Pasquale, Bart J. van Schravendijk
  • Patent number: 10056302
    Abstract: A semiconductor device may include a substrate, a p-channel device, and an n-channel device. The p-channel device may include a first metal member, a first dielectric layer positioned between the substrate and the first metal member, a first barrier layer positioned between the first dielectric layer and the first metal member, a first first-type work function layer directly contacting the first barrier layer and positioned between the first barrier layer and the first metal member, and a first second-type work function layer directly contacting both the first first-type work function layer and the first metal member. The n-channel device may include a second metal member, a second dielectric layer positioned between the substrate and the second metal member, and a second second-type work function layer directly contacting both the second dielectric layer and the second metal member.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: August 21, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Jie Zhao, Jia Lei Liu, Liang Wang
  • Patent number: 10050172
    Abstract: Fabrication of a heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can be epitaxially grown on a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 14, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Alexander Dobrinsky, Maxim S. Shatalov
  • Patent number: 10043785
    Abstract: A light emitting device includes a substrate, a plurality of micro light emitting chips and a plurality of conductive bumps. The substrate has a plurality of pads. The micro light emitting chips are disposed on the substrate in dispersion. Each of the micro light emitting chips includes an N-type semiconductor layer, an active layer and a P-type semiconductor layer. The conductive bumps are disposed corresponding to the micro light emitting chips and located between the micro light emitting chips and the substrate. The micro light emitting chips are electrically connected to the pads of the substrate by the conductive bumps. The orthogonal projection area of each of the conductive bumps on the substrate is 1.05 times to 1.5 times of the orthogonal projection area of each of the micro light emitting chips on the substrate.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: August 7, 2018
    Assignee: PlayNitride Inc.
    Inventors: Yu-Hung Lai, Tzu-Yang Lin
  • Patent number: 10038022
    Abstract: A light detector including an invisible light converting substrate, a light sensing element, a first protection layer, a thin film transistor, a first conductive pattern and a second protection layer is provided. The light sensing element and the thin film transistor are disposed on the invisible light converting substrate. The first protection layer covers the invisible light converting substrate and a second electrode of the light sensing element. The first protection layer has a via overlapped with the second electrode of the light sensing element. The first conductive pattern is disposed on the first protection layer and electrically connected to the second electrode of the light sensing element through the via of the first protection layer. The first conductive pattern is electrically connected between the second electrode of the light sensing element and a source of the thin film transistor.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: July 31, 2018
    Assignee: Au Optronics Corporation
    Inventors: Te-Ming Chen, Tsung-Han Chen, Sheng-Chen Wu, Geng-Qun Zhou, Ying-Hsien Chen
  • Patent number: 10020359
    Abstract: Capacitors and methods of forming the same include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Hemanth Jagannathan, Paul C. Jamison, John Rozen
  • Patent number: 10003185
    Abstract: An electrical device includes a first terminal structured to electrically connect to a power source; a second terminal structured to electrically connect to a load; a voltage sensor electrically connected to a point between the first and second terminals and being structured to sense a voltage at the point between the first and second terminals; a switch electrically connected between the first terminal and the second terminal; and a control unit structured to detect a power quality event in the power flowing between the first and second terminals based on the sensed voltage and to control a state of the switch based on the detected power quality event.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: June 19, 2018
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Charles John Luebke, Birger Pahl, Steven Christopher Schmalz
  • Patent number: 10002947
    Abstract: In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ming-Chyi Liu