Patents Examined by Lawrence Tynes, Jr.
  • Patent number: 9999136
    Abstract: The present invention concerns an electronic module with at least one component embedded in insulating material.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: June 12, 2018
    Assignee: GE Embedded Electronics Oy
    Inventor: Risto Tuominen
  • Patent number: 9997479
    Abstract: In a method for manufacturing a semiconductor device, a semiconductor substrate having a top surface is provided. A top metal layer is formed in the top surface. A first passivation layer is formed to cover the top metal layer and the top surface. The first passivation layer has a via hole exposing a portion of the top metal layer. A redistribution layer is formed to cover the first passivation layer, the portion of the top metal layer, and a side surface of the via hole. The redistribution layer includes an overhang structure over the via hole. An etching process is performed on the redistribution layer to remove the overhang structure and a portion of the redistribution layer to expose a portion of the first passivation layer. A second passivation layer is formed to cover the redistribution layer and the portion of the first passivation layer.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Hsien Lu, Chiang-Ming Chuang
  • Patent number: 9997688
    Abstract: A display apparatus and a method of manufacturing the same includes a plurality of light emitting diode modules each including a plurality of light emitting diodes regularly arranged therein, and a substrate including a drive unit driving the plurality of light emitting diodes. The substrate is coupled to the plurality of light emitting diode modules such that they oppose each other; and, the drive unit is electrically connected to the plurality of light emitting diodes.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 12, 2018
    Assignee: Seoul Semiconducter Co., Ltd.
    Inventors: Motonobu Takeya, Young Hyun Kim, Jong Ik Lee, Kwang Yong Oh
  • Patent number: 9991431
    Abstract: An optoelectronic component includes a carrier strip and an optoelectronic semiconductor chip, a first electrical connection surface formed on a front side of the chip and a second electrical connection surface is formed on a rear side of the chip, first and second electrically conductive contact regions are formed on the strip, the first region is arranged on a folding section of the strip, the rear side of the chip faces toward an upper side of the strip, the upper side faces toward the front side of the chip, the first electrical connection surface electrically conductively connects to the first region, the second electrical connection surface electrically conductively connects to the second region by a second connecting material, the strip has a second through-opening that lies next to the second region, and the second connecting material extends through the second contact opening to a lower side of the strip.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: June 5, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: David John Lacey, Abdul Manaf Shahrol Izzani
  • Patent number: 9983452
    Abstract: A method for detecting a substrate crack, a substrate, and a detection circuit. A non-closed test line having an opening is peripherally disposed along an edge of a glass substrate of a TFT substrate. Whether an edge of the TFT substrate has a crack or chip can be determined by measuring whether the test line is on or off. In this way, a detection omission can be avoided, detection efficiency is improved, and after the TFT substrate is used to assemble a liquid crystal module or the liquid crystal module is used to assemble a complete device, whether the edge of the TFT substrate in the liquid crystal module has a crack or chip can also be detected.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: May 29, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yanfeng Jia, Lei Tang, Pengfei Xie
  • Patent number: 9984995
    Abstract: A semiconductor package includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a top interposer. The first semiconductor chip and the second semiconductor chip are disposed on the package substrate. The top interposer is electrically connected to the first semiconductor chip and the second semiconductor chip, and the first semiconductor chip and the second semiconductor chip are present between the package substrate and the top interposer.
    Type: Grant
    Filed: November 13, 2016
    Date of Patent: May 29, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Patent number: 9984956
    Abstract: Provided are a through electrode including an organic side-wall insulating film, capable of eliminating a barrier layer and achieving satisfactory mechanical reliability and electrical reliability and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a through electrode disposed in a semiconductor substrate is provided, including: a copper layer in the semiconductor substrate; and a side-wall insulating film that is disposed between the copper layer and the semiconductor substrate so as to be in contact with the copper layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1).
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 29, 2018
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiro Aoyagi, Tung Thanh Bui, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi
  • Patent number: 9972800
    Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the dielectric layer. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. Metal contacts are formed on the channel material in the openings in the patterned resist layer and over portions of the patterned resist layer to protect sidewalls of the metal contacts to prevent degradation of the metal contacts.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: May 15, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shu-Jen Han, Jianshi Tang
  • Patent number: 9954093
    Abstract: A semiconductor device is manufactured by: i) forming a mask on a process surface of a semiconductor layer, elongated openings of the mask exposing part of the semiconductor layer and extending along a first lateral direction; ii) implanting dopants of a first conductivity type into the semiconductor layer based on tilt angle ?1 between an ion beam direction and a process surface normal and based on twist angle ?1 between the first lateral direction and a projection of the ion beam direction on the process surface; iii) implanting dopants of a second conductivity type into the semiconductor layer based on tilt angle ?2 between an ion beam direction and the process surface normal and based on twist angle ?2 between the first lateral direction and a projection of the ion beam direction on the process surface; and repeating i) to iii) at least one time.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 24, 2018
    Assignee: Infineon Technologies Austria AG
    Inventor: Hans Weber
  • Patent number: 9947784
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 17, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Patent number: 9947598
    Abstract: A methodology and associated wafer level assembly of testing crackstop structure designs. The wafer level semiconductor assembly includes: a substrate structure shaped to define a set of horizontal directions; a metallization layer located on top of the substrate structure, with the metallization layer including a crackstop structure formed therein in accordance with a crackstop structure design; and a tensioned layer located on top of the metallization layer, with the tensioned layer being made of material having internal tensile forces oriented in the horizontal directions. The tensile forces promote horizontal direction crack propagation in the metallization layer so that the crackstop structure design can be tested more rigorously and reliably before deciding on the crackstop design structure to put into mass production (which mass produced product would typically not include the tensioned layer).
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Krishna R. Tunga, Karen P. McLaughlin, Charles L. Arvin, Brian R. Sundlof, Steven P. Ostrander, Christopher D. Muzzy, Thomas A. Wassick
  • Patent number: 9941325
    Abstract: A method of manufacturing a solid-state image sensor, the method comprising preparing a structure including a substrate and an insulating member provided thereon, the substrate including a photoelectric conversion portion, forming a first opening in the insulating member, the first opening having a bottom face at a position higher than an upper face of the substrate and an inclined first face, forming a first member to fill the first opening, forming a second opening in the first member, forming a third opening, having a second face, in the insulating member by etching part of the insulating member under the second opening using the first member, and forming a second member to fill the third opening, wherein the inclined angle of the first face is smaller than that of the second face.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: April 10, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Shingo Kitamura
  • Patent number: 9935195
    Abstract: Semiconductor devices and methods of forming the same include forming semiconductor fins on a semiconductor substrate. A bottom source/drain region is formed in the semiconductor substrate. First charged dielectric spacers are formed on sidewalls of the semiconductor fins. A gate stack is formed over the bottom source/drain region. Second charged dielectric spacers are formed on sidewalls of the fin above the gate stack. The fins are recessed to a height below a top level of the second charged dielectric spacers. A top source/drain region is grown from the recessed fins.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: April 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Chun W. Yeung, Chen Zhang
  • Patent number: 9935056
    Abstract: A semiconductor chip having an improved structure without an investment in photolithography equipment, a method of manufacturing the semiconductor chip, and a semiconductor package and a display apparatus which include the semiconductor chip are described. The semiconductor chip includes a circuit region disposed in a central part of a rectangle that is elongated in a first direction. The circuit region includes a plurality of driving circuit cells disposed at predetermined intervals in the first direction. A plurality of electrode pads is disposed around the circuit region, and a process pattern is disposed at at least one of the four sides of the rectangle.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: April 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Myoung-soo Kim
  • Patent number: 9922874
    Abstract: A method of processing a semiconductor substrate includes: immersing a substrate in a first bath, wherein the substrate comprises a barrier layer, a conductive seed layer, and a patterned photoresist layer defining an opening; providing a first electric current between the conductive seed layer and a first anode disposed in electrical contact with the first bath to deposit a conductive material within the opening; stripping the patterned photoresist layer; immersing the substrate in a second bath; providing a second electric current that is a reverse of the first electric current between the conductive seed layer plus the conductive material and a second anode disposed in electrical contact with the second bath; etching the conductive seed layer from atop a field region of the barrier layer; and etching the barrier layer from atop a field region of the substrate.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: March 20, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prayudi Lianto, Sam Lee, Charles Sharbono, Marvin Louis Bernt, Guan Huei See, Arvind Sundarrajan
  • Patent number: 9923022
    Abstract: A method of fabrication of an array of optoelectronic structures. The method first provides a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells comprises an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portionsthat coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mattias B. Borg, Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Heike E. Riel, Heinz Schmid
  • Patent number: 9922899
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into the element chips by exposing the substrate to first plasma. Therefore, the element chips having a first surface, a second surface, and a side surface on which a plurality of convex portions are formed are held spaced from each other on a carrier. A protection film is formed on the side surface of the element chip by exposing the element chip to second plasma, at least convex portions formed on the side surface are covered by the protection film in the protection film formation, and creep-up of a conductive material to the side surface is suppressed in the mounting step.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: March 20, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Mitsuru Hiroshima, Mitsuhiro Okune
  • Patent number: 9905453
    Abstract: A protective sheeting for use in processing a semiconductor-sized wafer has a substantially circular base sheet and a substantially annular adhesive layer applied to a peripheral portion of a first surface of the base sheet. The inner diameter of the adhesive layer is smaller than the diameter of the wafer. Further, the outer diameter of the adhesive layer is larger than the inner diameter of an annular frame for holding the wafer. A related method includes attaching the protective sheeting to a front side or a back side of the wafer via the adhesive layer on the first surface of the base sheet so that an inner peripheral portion of the adhesive layer adheres to an outer peripheral portion of the front side or the back side of the wafer, and processing the wafer after the protective sheeting has been attached to the front side or the back side thereof.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: February 27, 2018
    Assignee: DISCO Corporation
    Inventor: Karl Heinz Priewasser
  • Patent number: 9893318
    Abstract: The present invention relates to an organic light-emitting diode, an array substrate and a preparation method thereof, and a display device. The organic light-emitting diode comprises an anode, a cathode, a light-emitting layer disposed between the anode and the cathode, and a hole injection layer disposed between the anode and the light-emitting layer, wherein the hole injection layer is provided therein with metal nanoparticles, and the frequency of a localized surface plasmon resonance of the metal nanoparticles is matched with the emission wavelength of the light-emitting layer. As the organic light-emitting diode is doped with metal nanoparticles in the hole injection layer and the resonance frequency of the localized surface plasmon of the metal nanoparticles is matched with the emission wavelength of the light-emitting layer, the metal nanoparticles are allowed to generate localized plasma resonance with photons, so that the light extraction efficiency of the organic light-emitting diode is enhanced.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 13, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qing Dai, Wenjun Hou, Ze Liu
  • Patent number: 9893155
    Abstract: Embodiments of the present invention are directed to semiconductor electronic devices formed of 2-D van der Waals material whose free charge carrier concentration is determined by adjacent semiconductor's polarization. According to one particular embodiment, a semiconductor electronic device is composed of one or more layers of two dimensional (2-D) van der Waals (VDW) material; and one or more layers of polarized semiconductor material adjacent to the one or more layer of 2-D VDW material. The polarization of the adjacent semiconductor material establishes the free carrier charge concentration of the 2-D VDW material.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 13, 2018
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Pankaj B Shah