Patents Examined by Lawrence Tynes, Jr.
  • Patent number: 9887285
    Abstract: A semiconductor device comprises a silicon carbide layer, a first electrode, a second electrode, and a gate. The silicon carbide layer has first region of first conductivity type between the first and second electrodes and also the gate and second electrode. A second region of the first type is between the first electrode and the first region. A third region of second conductivity type is between the first electrode and the second region. A fourth region of the first type is between the first electrode and the third region. A fifth region of the first type is between the gate and the second region. The third region is between the fourth and fifth regions. A sixth region of the first type contacts the first electrode and is between the second region and this electrode. An insulation layer is between the gate and the third region and also the fifth region.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: February 6, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Oota, Masaru Furukawa
  • Patent number: 9884756
    Abstract: A MEMS device comprises a first layer (1), a second layer (2) and a third layer (3) sealed together. A mobile structure (7.1, 7.2) in the second layer (2) is defined by openings (8.1, 8.2) in the second layer (2). In the first layer (1), there is at least one first-layer cavity (6.1, 6.2) with an opening towards the mobile structure (7.1, 7.2) of the second layer (2). In the third layer (3), there is at least one third-layer cavity (9) with an opening towards the mobile structure (7.1, 7.2) of the second layer (2). Therefore, the third-layer cavity (9) and the second layer (2) define a space within the MEMS device, A getter layer (10.1, 10.2) arranged on a surface of said space. The getter layer (10.1, 10.2) is preferably arranged on a surface of the second layer (2) and in particular, the getter layer (10.1, 10.2) is arranged on a static part of the second layer (2). Alternatively, the MEMS device has a third-layer cavity (24) with at least two recesses (25.1, 25.2, 25.3) and the getter layer (26.1, 26.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: February 6, 2018
    Assignee: TRONICS MICROSYSTEMS S.A.
    Inventors: Julien Cuzzocrea, Joël Collet
  • Patent number: 9887258
    Abstract: A method for fabricating a capacitor includes following steps: providing a substrate and a first conducting material layer which is disposed on the substrate; removing a part of the first conducting material layer to expose a part of the substrate to form a plurality of first inner electrodes, wherein the first inner electrodes are arranged along a first direction, and the adjacent first inner electrodes have an interval therebetween; forming a dielectric layer along a second direction by a chemical vapor deposition process, wherein the first direction is perpendicular to the second direction so that the dielectric layer covers the first inner electrodes and the exposed part of the substrate, and the dielectric layer does not fully fill the intervals; and forming a second conducting material layer to fill the intervals that are not fully filled by the dielectric layer to form a plurality of second inner electrodes.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: February 6, 2018
    Assignee: ASUSTeK COMPUTER INC.
    Inventor: Bin-Yi Lin
  • Patent number: 9871141
    Abstract: A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon layer over the silicon germanium layer, and performing a first oxidation to oxidize the silicon germanium layer, wherein first silicon germanium oxide regions are generated. A strain releasing operation is performed to release a strain caused by the first silicon germanium oxide regions. A gate dielectric is formed on a top surface and a sidewall of the silicon layer. A gate electrode is formed over the gate dielectric.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Carlos H. Diaz, Chih-Hao Wang, Gwan Sin Chang, Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
  • Patent number: 9871115
    Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
  • Patent number: 9865638
    Abstract: A semiconductor device includes a first semiconductor substrate having a first wiring layer which includes a first conductive pad, a second semiconductor substrate disposed on the first semiconductor substrate and including a second wiring layer which includes a second conductive pad, a first oxide layer disposed on the second semiconductor substrate and containing a second end of an intermediate connection which extends vertically through the second semiconductor substrate and has a first end electrically connected to the second conductive pad, and a third semiconductor substrate disposed on the first oxide layer and including a third wiring layer which includes a third conductive pad. The second end of the intermediate connection layer is electrically connected to the third conductive pad via a metal bond.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: January 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Doo Won Kwon
  • Patent number: 9859113
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The semiconductor device structure includes spacers over opposite sidewalls of the gate stack. The spacers and the gate stack surround a recess over the gate stack. The semiconductor device structure includes a first insulating layer over the gate stack and an inner wall of the recess. The semiconductor device structure includes a second insulating layer over the first insulating layer. Materials of the first insulating layer and the second insulating layer are different, and a first thickness of the first insulating layer is less than a second thickness of the second insulating layer.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Yang Li, Chun-Sheng Wu, Ding-I Liu, Yi-Fang Li
  • Patent number: 9837522
    Abstract: There are disclosed herein various implementations of a III-Nitride bidirectional device. Such a bidirectional device includes a substrate, a back channel layer situated over the substrate, and a device channel layer and a device barrier layer situated over the back channel layer. The device channel layer and the device barrier layer are configured to produce a device two-dimensional electron gas (2DEG). In addition, the III-Nitride bidirectional device includes first and second gates formed on respective first and second depletion segments situated over the device barrier layer. The III-Nitride bidirectional device also includes a back barrier situated between the back channel layer and the device channel layer. A polarization of the back channel layer of the III-Nitride bidirectional device is substantially equal to a polarization of the device channel layer.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: December 5, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Haeberlen
  • Patent number: 9837483
    Abstract: An electrical device includes a current transport layer made of an anomalous Hall material. The electrical device also includes a first ferromagnetic island in physical contact with the current transport layer and a second ferromagnetic island in physical contact with the current transport layer, the second ferromagnetic island oriented with respect to the first ferromagnetic island such as to concentrate a magnetic field, generated by current flow along a conducting surface of the anomalous Hall material, over the first ferromagnetic island and the second ferromagnetic island.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: December 5, 2017
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Matthew J. Gilbert, Timothy M. Philip, Daniel Somerset Green
  • Patent number: 9837505
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9831085
    Abstract: Provided are a method of fabricating a hafnium oxide layer and a method of fabricating a semiconductor device using the same. The method of fabricating a tetragonal hafnium oxide layer includes providing a substrate and then forming an initial hafnium oxide layer on the substrate. The initial hafnium oxide layer may have an amorphous structure, a monoclinic crystal structure, or a mixed structure thereof on the substrate. Phase-changing the initial hafnium oxide layer to a tetragonal hafnium oxide layer by heating the initial hafnium oxide layer at a temperature equal to or higher than a phase change temperature to the tetragonal hafnium oxide layer, is performed. Then, the heated tetragonal hafnium oxide layer may be rapidly cooled to suppress nucleation and growth of a monoclinic hafnium oxide in the tetragonal hafnium oxide layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: November 28, 2017
    Assignee: SK Hynix Inc.
    Inventors: Deok Sin Kil, Jae Sung Roh
  • Patent number: 9825118
    Abstract: A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chung Chen, Shu Fang Fu, Chang-Sheng Liao
  • Patent number: 9818810
    Abstract: An OLED and a fabrication method thereof, and a display apparatus are provided. The OLED comprises: a base substrate; a first electrode, an organic functional layer and a transparent or semi-transparent second electrode sequentially disposed on the base substrate; and a covering layer provided on a side of the second electrode away from the base substrate. A surface of the covering layer away from the base substrate is uneven.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: November 14, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Wenyu Ma
  • Patent number: 9812441
    Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: November 7, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Koichi Taniguchi, Masato Maede
  • Patent number: 9806088
    Abstract: A semiconductor memory device includes a substrate, a plurality of insulating layers and wiring layers that are alternately formed, and a plurality of first layers and second layers that are alternately formed. The substrate has a memory region extending in first and second directions along a surface of the substrate, a step region adjacent to the memory region in the first direction, and a peripheral region adjacent to the memory region and the step region in the second direction. The insulating layers and the wiring layers are formed on the memory region and the step region. The first and second layers are formed on the peripheral region. Each of the first layers is formed on a same level as and in contact with one of the insulating layers, and each of the second layers is formed on a same level as and in contact with one of the wiring layers.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: October 31, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Takuya Inatsuka
  • Patent number: 9799524
    Abstract: A field effect transistor (FET) with raised source/drain region of the device so as to constrain the epitaxial growth of the drain region. The arrangement of the spacer layer is created by depositing a photoresist over the extended drain layer during a photolithographic process.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 24, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Akira Ito, Shom Ponoth
  • Patent number: 9799633
    Abstract: A semiconductor light source comprising first and second light-emitting diode chips; and a conversion element containing a first phosphor and a second phosphor, wherein the conversion element is disposed downstream of the first and second light-emitting diode chips. The first light-emitting diode chip emits electromagnetic radiation with a first emission maximum. The second light-emitting diode chip emits electromagnetic radiation with a second emission maximum. The first phosphor has a first absorption maximum and a first radiating maximum. The second phosphor has a second absorption maximum, which differs from the first absorption maximum, and a second radiating maximum, which differs from the first radiating maximum. The degree of conversion of the first phosphor for the electromagnetic radiation of the first light-emitting diode chip is greater than the degree of conversion of the second phosphor for the electromagnetic radiation of the first light-emitting diode chip.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: October 24, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Ales Markytan, Christian Gärtner
  • Patent number: 9793233
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventors: Rajasekaran Swaminathan, Leonel R. Arana, Yoshihiro Tomita, Yosuke Kanaoka
  • Patent number: 9793248
    Abstract: A light emitting device includes a substrate, a plurality of micro light emitting chips and a plurality of conductive bumps. The substrate has a plurality of pads. The micro light emitting chips are disposed on the substrate in dispersion. Each of the micro light emitting chips includes an N-type semiconductor layer, an active layer and a P-type semiconductor layer. The conductive bumps are disposed corresponding to the micro light emitting chips and located between the micro light emitting chips and the substrate. The micro light emitting chips are electrically connected to the pads of the substrate by the conductive bumps. An orthogonal projection area of each of the conductive bumps on the substrate is greater than an orthogonal projection area of each of the micro light emitting chips on the substrate.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 17, 2017
    Assignee: PlayNitride Inc.
    Inventors: Yu-Hung Lai, Tzu-Yang Lin
  • Patent number: 9793218
    Abstract: In a method for manufacturing a device embedded substrate, a conductive via that penetrates a first insulating layer and a second insulating layer from an outer metal layer to reach a second terminal of an IC device is formed after forming the outer metal layer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: October 17, 2017
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Mitsuaki Toda, Tohru Matsumoto, Seiko Murata