Abstract: Provided is a highly reliable light-emitting device in which a light-emitting element is prevented from being damaged when external physical force is applied. The light-emitting device includes a light-emitting element formed over a first substrate, including a first electrode layer, a light-emitting layer, and a second electrode layer; a structure body formed over the first substrate; a second substrate provided to face the first substrate; and a bonding layer provided between the first substrate and the second substrate. The light-emitting layer is separated by the structure body. By strengthening adhesion between the structure body and the bonding layer, or between the structure body and the second electrode, the highly reliable light-emitting device in which damage of the light-emitting element is prevented can be provided.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming an interfacial layer material over a semiconductor substrate and forming a gate insulation layer over the interfacial layer material that includes a combination of a layer of a hafnium oxide material and a layer of hafnium silicate material. The layer of the hafnium silicate material includes less than about 40 % of an overall height of the gate insulation layer.

Abstract: The present technology provides a color-sensing device that includes an electrically-conductive substrate and a bulk heterojunction (BHJ) polymer layer formed on the substrate. The color-sensing device is configured to detect a first color of two colors and produce a first electrical signal that includes a first current response indicating detection of the first color. The color-sensing device is further configured to detect a second color of the two colors and produce a second electrical signal that includes a second current response indicating detection of the second color.

Abstract: An integrated circuit (IC) device includes an IC die and encapsulation material surrounding the IC die. A first set of leads is coupled to the IC die and has first contact pads exposed on a bottom surface of the encapsulation material adjacent its periphery. A second set of leads is coupled to the IC die and has second contact pads exposed on the bottom surface of the encapsulation material adjacent its periphery. The second set of leads has internal ends extending laterally inwardly from respective ones of the second contact pads to define a die pad area supporting the IC die.

Abstract: A high voltage metal-oxide-metal (HV-MOM) device includes a substrate, a deep well in the substrate and at least one high voltage well in the substrate over the deep well. The HV-MOM device further includes a dielectric layer over each high voltage well of the at least one high voltage well and a gate structure over the dielectric layer. The HV-MOM device further includes an inter-layer dielectric (ILD) layer over the substrate, the ILD layer surrounding the gate structure. The HV-MOM device further includes a first inter-metal dielectric (IMD) layer over the ILD layer and a first metal feature in the first IMD layer, wherein the first metal feature is part of a MOM capacitor.

Abstract: An organic light emitting display device, including: a substrate; a display unit formed on the substrate; and an encapsulation layer formed on the display unit, in which the encapsulation layer includes a lower layer formed on the display unit, at least one pattern layer formed on the lower layer, and an upper layer formed on the pattern layer, and the lower layer includes at least one of an inorganic film and an organic film, and the pattern layer includes an uneven pattern having a plurality of protrusions which are spaced apart from each other, formed on the lower layer, and a filling layer disposed on the uneven pattern, and the upper layer includes at least one of an inorganic film and an organic film.

Abstract: A support for an optoelectronic semiconductor chip includes a support body with a first main face and a second main face opposite the first main face, at least one electrical plated-through hole extending from the first main face to the second main face and formed in the support body, and an insulating layer arranged on the first main face, the insulation layer covering the electrical plated-through hole only in regions.

Abstract: An integrated circuit electrical protection device includes a semiconductor substrate, and first, second, and third doped regions of a first polarity in the semiconductor substrate. The first and second doped regions are separated from one another by a first body region having a second polarity and the second and third doped regions are separated from one another by a second body region having the second polarity. The first and second polarities are different from one another. A fourth doped region of the second polarity directly abutting and in contact with the third doped region. A first gate structure is formed over the first body region between the first and second doped regions. A second gate structure is formed over the second body region between the second and third doped regions.

Abstract: A semiconductor memory cell array is disclosed that includes a memory cell unit. The memory cell unit includes an active region, a first transistor, a second transistor, a gate structure, and an interconnect. The first transistor and the second transistor are formed on the active region. The gate structure is formed on the active region and between the first transistor and the second transistor. The interconnect connects the gate structure and at least one of sources of the first transistor and the second transistor to a power line.

Abstract: A method of forming a semiconductor structure can include forming a photolithography mask on a silicon fin having a hard mask layer thereon extending in a first direction. A trench can be formed through the hard mask layer into the silicon fin using the photolithography mask, where the trench extends in a second direction to separate the silicon fin into first and second fin structures extending end-to-end in the first direction. A portion of the trench formed by the hard mask layer can be widened relative to a lower portion of the trench defined by the first and second fin structures.

Abstract: A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.

Abstract: A printed wiring board having a land for surface-mounting of an electronic component, includes the land having a pair of land pieces arranged in an opposing manner, and each of the land pieces including a plurality of land portions having widths different from each other, and a coupling portion partially coupling a boundary portion between a pair of adjacent ones of the land portions.

Abstract: An optical sensor chip device and a corresponding production method. The optical sensor chip device includes a substrate having a front side and a rear side; at least one first optical sensor chip for acquiring a first optical spectral range, the chip being attached to the substrate; and a first sealed cavern fashioned above an upper side of the first optical sensor chip. The first optical sensor chip is situated on a first side of the first cavern, and a first optical device is situated on an opposite, second side of the first cavern.

Abstract: Substrates (wafers) with uniform backside roughness and methods of manufacture are disclosed. The method includes forming a material on a backside of a wafer. The method further includes patterning the material to expose portions of the backside of the wafer. The method further includes roughening the backside of the wafer through the patterned material to form a uniform roughness.

Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a plurality of first electrodes provided on the first insulating film, a second insulating film provided on a side surface of the first electrodes and on an upper surface of the first electrodes, and a second electrode insulated from the first electrodes by the second insulating film. The second electrode includes an interconnect portion provided on the second insulating film, and a downward-extending portion extending into a space between the first electrodes from the interconnect portion. A lower end portion of the downward-extending portion is not covered with the second insulating film.

Abstract: In one embodiment, a method of making a VDMOS transistor can include: (i) etching an oxide layer formed on a surface of an epitaxial structure to define an active region of the VDMOS; (ii) injecting and diffusing a first dopant into the active region to form a doping region; (iii) forming a gate oxide layer on the active region; (iv) depositing polysilicon on the gate oxide layer, and etching the polysilicon to form a gate; (v) injecting a second dopant at an end of the gate to form a source, where the first and second dopants have opposite types; (vi) forming a contact hole adjacent to the gate, and injecting a third dopant into the contact hole, where the first and third dopants have a same type; (vii) depositing and etching aluminum on a chip surface; and (viii) coating the aluminum and chip surface with a passivation layer.

Abstract: Occurrence of a crosstalk phenomenon in a light-emitting device is inhibited. A light-emitting device including an insulating layer 416; a first lower electrode 421a formed over the insulating layer; a second lower electrode 421b formed over the insulating layer; a partition 418 formed over the insulating layer and positioned between the first lower electrode and the second lower electrode; a stacked-layer film 423 which is formed over the first lower electrode, the partition, and the second lower electrode and includes a light-emitting layer containing a light-emitting substance and a layer having higher conductivity than that of the light-emitting layer; an upper electrode 422 formed over the stacked-layer film; and a shield electrode 419 which is formed under the partition and does not overlap with the first lower electrode and the second lower electrode.

Abstract: A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.

Abstract: A nitride semiconductor structure of the present invention is obtained by growing an h- or t-BN thin film (12) and a wurtzite-structure AlxGa1-xN (x>0) thin film (14) as buffer layers and forming a single-crystal wurtzite-structure AlGaInBN thin film (13) thereon. While GaN, AlGaN, AlN, and the like have the wurtzite structure with sp3 bonds, h-BN or t-BN has the graphite structure with sp2 bonds, and has a completely different crystal structure. Accordingly, it has heretofore not been considered that a wurtzite-structure AlGaInBN thin film can be grown on a graphite-structure h-BN thin film. However, when a wurtzite-structure AlxGa1-xN (x>0) thin film (14) is formed as a buffer layer on a graphite-structure boron nitride thin film (12), a wurtzite-structure AlGaInBN (13) nitride semiconductor structure such as GaN can be grown on the buffer layer.

Abstract: A light-emitting device having a through-hole cavity is disclosed. The optical device may contain a plurality of conductors, a light source die, a body and a transparent encapsulant material. The body may have a top surface and a bottom surface. A cavity is formed within the body extending from the bottom surface to the top surface and defining therein a bottom opening and a top opening, respectively. Optionally, the light-emitting device may comprise a lens. During manufacturing process, liquid or semi-liquid form transparent material is injected from the bottom surface into the cavity, encapsulating the light source die and forming a lens. The shape of the lens is defined by a mold aligned to the top opening of the body. In yet another embodiment, optical devices having a cavity or multiple cavities are disclosed. The optical devices may include a proximity sensor, an opto-coupler, an encoder and other similar sensors.