Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures, and an etch buffer layer. The etch buffer layer includes an overhang component disposed on the upper portion of the gate structures with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent gate structures.

Abstract: A display device related to one embodiment of the present invention includes a first substrate arranged with a plurality of pixels in the shape of a matrix, an insulation film arranged above the first substrate, a first electrode arranged above the insulation film, a second electrode arranged on an upper layer of the first electrode, and an organic EL layer arranged between the first electrode and the second electrode, wherein the insulation film includes a plurality of concave parts arranged corresponding to each of the plurality of pixels on the side of the first electrode, the first electrode, the organic EL layer and the second electrode are stacked in order above the insulation film and the concave part, and the an insulation layer is covering an end part of the first electrode arranged above the concave part is arranged on an interface part sectioning each of the plurality of pixels.

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

Abstract: A transistor includes a substrate and a buffer layer on the substrate, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and a back-barrier layer between a first portion of the channel layer and a second portion of the channel layer. The back-barrier layer has a band gap discontinuity with the channel layer. The transistor further includes an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer. The transistor further includes a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the active layer.

Abstract: A solid-state imaging device includes a photoelectric conversion device that includes a non-chalcopyrite-based compound semiconductor of at least one layer, which is lattice bonded or pseudo lattice bonded, and is formed on a silicon substrate, and a chalcopyrite-based compound semiconductor of at least one layer which is formed on the non-chalcopyrite-based compound semiconductor.

Abstract: A power module includes a substrate DMB (Direct Metal Bonded). A novel bridging DMB is surface mounted to the substrate DMB along with power semiconductor device dice. The top metal layer of the bridging DMB has one or more islands to which bonding wires can connect. In one example, an electrical path extends from a module terminal, through a first bonding wire and to a first location on a strip-shaped island, through the island to a second location, and from the second location and through a second bonding wire. The strip-shaped island of the bridging DMB serves as a section of the overall electrical path. Another bonding wire of a separate electrical path passes transversely over the strip-shaped island without any wire crossing any other wire. Use of the bridging DMB promotes bonding wire mechanical strength as well as heat sinking from bonding wires down to the substrate DMB.

Abstract: An electronic device including a semiconductor memory includes a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate.

Abstract: MOS transistors and fabrication methods are provided. An exemplary MOS transistor includes a gate structure formed on a semiconductor substrate. A lightly doped region is formed by a light ion implantation in the semiconductor substrate on both sides of the gate structure. A first halo region is formed by a first halo implantation to substantially cover the lightly doped region in the semiconductor substrate. A groove is formed in the semiconductor substrate on the both sides of the gate structure. Prior to forming a source and a drain in the groove, a second halo region is formed in the semiconductor substrate by a second halo implantation performed into a groove sidewall that is adjacent to the gate structure. The second halo region substantially covers the lightly doped region in the semiconductor substrate and substantially covers the groove sidewall that is adjacent to the gate structure.

Abstract: A semiconductor module includes a first semiconductor chip including a first signal line and a first ground, a mounting board or a second semiconductor chip including a second signal line and a second ground, a signal line coupling bump that couples the first signal line and the second signal line with each other, a first ground coupling bump that couples the first ground and the second ground with each other, a signal line side insulating film including a capacitance that causes a series resonance with an inductance by the signal line coupling bump at a target frequency and a ground side insulating film including a capacitance that causes a series resonance with an inductance by the first ground coupling bump at a target frequency.

Abstract: Disclosed herein is a waterproof case for protecting electronic devices. The waterproof case includes a flexible waterproof bag attached to a rigid lid that can be opened to allow electronic devices to pass into the bag. When closed, the lid forms a watertight seal that protects the inside of the bag from ingress of water. The lid can include a pass-through jack which allows a user to connect an electronic device, such as an audio device, to an output through the lid. The case may also be incorporated into a flexible attachment system, such as an armband or swimbelt. Methods of connecting an electronic device to an electronic output, such as an audio output, through a waterproof case are also provided.

Abstract: A thin film, a method of forming the thin film, a semiconductor device including the thin film, and a method of manufacturing the semiconductor device include forming a thin film including a metal oxynitride, and treating the thin film with inert gas ions so as to stabilize properties of the thin film. The metal oxynitride may include zinc oxynitride (ZnOxNy). The inert gas ions may include at least one of Ar ions and Ne ions. The treating of the thin film with the inert gas ions may be performed by a sputtering process, a plasma treatment process, or the like.

Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.

Abstract: An active matrix organic light-emitting diode array substrate, a manufacturing method thereof and a display device including the same are disclosed to improve the aperture ratio of pixel of the array substrate and the display quality of the display device. The array substrate includes: a substrate; and a plurality of pixel units located on the substrate and arranged in array manner, each of the pixel units comprising a thin film transistor, a first transparent electrode, a second transparent electrode and a gate insulation layer provided between the first transparent electrode and the second transparent electrode. The first transparent electrode is provided on the substrate and is electrically connected to a gate of the thin film transistor; and the second transparent electrode is electrically connected to a drain of the thin film transistor, and the second transparent electrode is positioned opposite to the first transparent electrode to form a storage capacitor of the pixel unit therebetween.

Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.

Abstract: Packages substrates are provided. The package substrates may include a substrate and a set of leads disposed on the substrate. The set of lead may include a first lead, a second lead and a third lead, which are sequentially disposed along a first direction. Each of the first lead, the second lead and the third lead may extend along a second direction that is different from the first direction. The first lead and the second lead may be spaced apart at a first distance, and the second lead and the third lead may be spaced apart at a second distance that is less than the first distance.

Abstract: A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support substrate supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate. A transistor element is formed in the element region, the transistor element having a transistor buried impurity layer formed within the active layer. The semiconductor device further includes a substrate contact having a contact buried impurity layer formed within the contact region and a through contact extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer, the contact buried impurity layer being in the same layer as the transistor buried impurity layer.

Abstract: A method of manufacturing a circuit board may include: preparing a circuit board body including an insulating layer having a first surface and a second surface opposite to the first surface and a first conductive thin film layer disposed on the first surface of the insulating layer and having a convex portion which is disposed on a first surface of the first conductive thin film layer and is embedded in the insulating layer; removing the convex portion to form a cavity corresponding to the convex portion in the insulating layer; and forming one or more first wiring patterns on the first surface of the insulating layer by removing first portions of the first conductive thin film layer. The one or more first wiring patterns correspond to second portions of the first conductive thin film layer not removed.

Abstract: Structures and formation methods of a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a substrate and a MEMS structure over the substrate, and the MEMS structure has a movable element. The movable element is surrounded by a cavity. The MEMS device also includes a fuse layer on the movable element.

Abstract: A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon layer over the silicon germanium layer, and performing a first oxidation to oxidize the silicon germanium layer, wherein first silicon germanium oxide regions are generated. A strain releasing operation is performed to release a strain caused by the first silicon germanium oxide regions. A gate dielectric is formed on a top surface and a sidewall of the silicon layer. A gate electrode is formed over the gate dielectric.