Abstract: A light emitting chip of the present invention includes a device chip having a sapphire substrate and a light emitting layer formed over the front surface of the sapphire substrate and a transparent member bonded to the back surface of the sapphire substrate by a resin transmissive to emitted light from the light emitting layer. The transparent member is transmissive to the emitted light from the light emitting layer. A groove is formed in an abutting surface of the transparent member against the device chip in such a manner as to be exposed to the side surface and the abutting surface of the transparent member. The groove width of the groove is smaller than the length of one side of the device chip.

Abstract: In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins.

Abstract: According to one embodiment, a semiconductor device includes a MRAM chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer separated from the MRAM chip, surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path.

Abstract: According to one embodiment, a photodiode includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a film. The second semiconductor layer is provided in the first semiconductor layer. The third semiconductor layer is provided in the first semiconductor layer so as to surround the second semiconductor layer. Each of one ends of the second and third semiconductor layers is located at an upper surface of the first semiconductor layer. The first to third semiconductor layers include first to third impurity concentrations respectively. The second and third impurity concentrations are higher than the first impurity concentration. The film is provided above the third semiconductor layer, and blocks light to enter into a neighborhood of the third semiconductor layer.

Abstract: Magnetic spin-torque memory cells, often referred to as magnetic tunnel junction cells, which have magnetic anisotropies (i.e., magnetization orientation at zero field and zero current) of the associated ferromagnetic layers aligned perpendicular to the wafer plane, or “out-of-plane”. A memory cell may have a ferromagnetic free layer, a first pinned reference layer and a second pinned reference layer, each having a magnetic anisotropy perpendicular to the substrate. The free layer has a magnetization orientation perpendicular to the substrate that is switchable by spin torque from a first orientation to an opposite second orientation.

Abstract: A method of fabricating an electronic apparatus includes forming an active layer over a wafer, forming a backscatter layer over the wafer, and directing radiation toward the wafer to anneal the active layer. The backscatter layer is not transparent to the radiation, more reflective than absorptive of the radiation, and positioned such that the backscatter layer inhibits exposure of the wafer to the radiation apart from the active layer.

Abstract: A capacitor suitable for inclusion in a semiconductor device includes a substrate, a first metallization level, a capacitor dielectric, a capacitor plate, an interlevel dielectric layer, and a second metallization level. The first metallization level overlies the substrate and includes a first metallization plate overlying a capacitor region of the substrate. The capacitor dielectric overlies the first metallization plate and includes a dielectric material such as a silicon oxide or silicon nitride compound. The capacitor plate is an electrically conductive structure that overlies the capacitor dielectric. The interlevel dielectric overlies the capacitor plate. The second metallization layer overlies the interlevel dielectric layer and may include a second metallization plate and a routing element. The routing element may be electrically connected to the capacitor plate. The metallization plates may include a fingered structure that includes a plurality of elongated elements extending from a cross bar.

Abstract: A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.

Abstract: Provided are an organic light emitting diode, an organic light emitting display panel including the same, and a method of manufacturing the organic light emitting display panel. The organic light emitting diode includes: an anode electrode on a substrate; a first common layer on the anode electrode to inject or transport holes and having a non-flat side; an organic light emitting layer on the first common layer; a planarization layer on the non-flat side of the first common layer, providing a flat side to the organic light emitting layer, transporting holes from the first common layer to the organic light emitting layer, and including perfluorocyclobutanes (PFCBs); and a cathode electrode on the organic light emitting layer.

Abstract: A method of forming a semiconductor device includes forming an opening having a sidewall in a substrate and forming a first epitaxial layer in the opening. The first epitaxial layer is formed in a first portion of the sidewall without growing in a second portion of the sidewall. A second epitaxial layer is formed in the opening after forming the first epitaxial layer. The second epitaxial layer is formed in the second portion of the sidewall. The first epitaxial layer is removed after forming the second epitaxial layer.

Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.

Abstract: A mechanism is provided for reducing stiction in a MEMS device by forming a near-uniform silicon carbide layer on silicon surfaces using carbon from TEOS-based silicon oxide sacrificial films used during fabrication. By using the TEOS as a source of carbon to form an antistiction coating, all silicon surfaces can be coated, including those that are difficult to coat using standard self-assembled monolayer (SAM) processes (e.g., locations beneath the proof mass). Controlled processing parameters, such as temperature, length of time for annealing, and the like, provide for a near-uniform silicon carbide coating not provided by previous processes.

Abstract: In a nitride-based semiconductor device, an undoped gallium nitride (GaN) layer is formed on an aluminum gallium nitride (AlGaN) layer, and a silicon carbon nitride (SixC1-xN) functional layer is formed on the undoped GaN layer.

Abstract: In some embodiments, a normally on high voltage switch device (“normally on switch device”) incorporates a trench gate terminal and buried doped gate region. In other embodiments, a surface gate controlled normally on high voltage switch device is formed with trench structures and incorporates a surface channel controlled by a surface gate electrode. The surface gate controlled normally on switch device may further incorporate a trench gate electrode and a buried doped gate region to deplete the conducting channel to aid in the turning off of the normally on switch device. The normally on switch devices thus constructed can be readily integrated with MOSFET devices and formed using existing high voltage MOSFET fabrication technologies.

Abstract: There are provided a semiconductor package and a manufacturing method thereof, capable of increasing integration by mounting electronic devices on both surfaces of a substrate. The semiconductor package includes a first substrate having mounting electrodes on both surfaces thereof; a plurality of electronic devices mounted on both surfaces of the first substrate; and a second substrate exposed in cavities and bonded to a bottom surface of the first substrate so as to accommodate the electronic devices mounted on the bottom surface of the first substrate in the cavities.

Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface. The electronic device can further include first conductive structures within each of a first trench and a second trench, a gate electrode within the first trench and electrically insulated from the first conductive structure, a first insulating member disposed between the gate electrode and the first conductive structure within the first trench, and a second conductive structure within the second trench. The second conductive structure can be electrically connected to the first conductive structures and is electrically insulated from the gate electrode. The electronic device can further include a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench. Processing sequences can be used that simplify formation of the features within the electronic device.

Abstract: Methods of forming a power semiconductor device having an edge termination are provided in which the power semiconductor device that has a drift region of a first conductivity type is formed on a substrate. A junction termination extension is formed on the substrate adjacent the power semiconductor device, the junction termination extension including a plurality of junction termination zones that are doped with dopants having a second conductivity type. The junction termination zones have different effective doping concentrations. A dopant activation process is performed to activate at least some of the dopants in the junction termination zones. An electrical characteristic of the power semiconductor device is measured. Then, the junction termination extension is etched in order to reduce the effective doping concentration within the junction termination extension.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)?0.7, and rb/Rb<1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion.

Abstract: The present application relates to a light emitting device package. The light emitting device package includes a package substrate in which a via hole is formed. An electrode layer extends to both surfaces of the package substrate after passing through the via hole. A light emitting device is arranged on the package substrate and is connected to the electrode layer. A fluorescence film includes a first part that fills at least a part of an internal space of the via hole and a second part that covers at least a part of the light emitting device.

Abstract: A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.