Abstract: A fishing lure power charging device includes a body. A circuit board is assembled in the body. The circuit board has a power switching circuit and a charging circuit. A light emitter is assembled in the body and electrically connected to the power switching circuit, so that the light emitter emits light when the light emitter is electrically conducted. A battery is assembled in the body and electrically connected to the charging circuit, so that the battery is chargeable. Two conductive members are electrically connected to the circuit board, separately assembled to the body, and exposed from the body. A light sensing switch is assembled to the body and electrically connected to the circuit board, so that the light sensing switch switches the two conductive members to conduct with the power switching circuit or the charging circuit based on the light illuminating on the light sensing switch.

Abstract: In a method for modeling electromagnetic effects in a planar circuit that employs a plurality of through-silicon vias in a domain, a region around each through-silicon via is described in terms of a cylindrical accumulation mode basis function. The cylindrical accumulation mode basis function is incorporated into an equivalent circuit that describes selected electrical characteristics of each through-silicon via. A plurality of localized intervals around each through-silicon via is selected. A multilayer Green's function is approximated for IMNzz? (wherein M and N identify selected layers and wherein zz? designates layer boundaries in a layer through which the through-silicon via passes) in each localized interval without approximating the Green's function over the entire domain. Coefficients IMNzz? are approximated over a predetermined range of frequencies (?). Admittance parameters based on of IMNzz? are calculated over a frequency sweep.

Abstract: A solar electric system comprises photovoltaic elements having integrated energy storage and control, ideally on each PV-panel. The energy storage media may be primary or secondary cylindrical cells interconnected into a battery and/or an array of capacitors (or super-capacitors) and are accompanied by an electronic control circuit which may perform a variety of functions, including but not limited to power quality control, load following, pulse powering, active line transient suppression, local sensing, remote reporting, wireless or wired communications allowing two way programmable control through local or remote operation. The operation of the system may yield direct current or with the integration of bidirectional micro-inverters create distributed alternating current generation enhanced with energy storage and control two way energy flows between the solar system and the grid.

Abstract: Various techniques are provided to implement a logical memory in programmable logic devices (PLDs) having embedded block RAMs (EBRs). For example, a computer-implemented method includes determining a main area of a logical memory that can be fully mapped to a first one or more EBRs configured in a first depth-width configuration, mapping the main area to the first one or more EBRs, and mapping the remainder of the logical memory to a second one or more EBRs configured in a second or more depth-width configurations. The mapping of the remainder of the logical memory may be performed hierarchically by a recursive process, in some embodiments. The depth-width configurations and the corresponding mapping may be selected according to an efficiency metric, for example. Other embodiments include a system comprising a PLD and a configuration memory storing configuration data generated by such a method, and a PLD configured with such configuration data.

Abstract: Disclosed is an approach to implement a requirements-driven analog verification flow. Disparate islands of verification tasks are performed with individual cellviews to be set into an overarching and closed loop verification flow context for a project or a complex verification task.

Abstract: In one embodiment, a writing data verification method is for verifying a conversion error due to data conversion from first writing data in a vector format based on design data to second writing data in a pixel format. The method includes converting the second writing data to third writing data in a vector format, performing an exclusive OR operation on the first writing data and the third writing data, enlarging a graphic of the first writing data to obtain an enlarged graphic and generating a tolerance region graphic from a difference between the enlarged graphic and the graphic of the first writing data, and detecting a defect by performing a mask process on a graphic generated by the exclusive OR operation with the tolerance region graphic.

Abstract: A method may include: specifying a random nets credit (RNC) statistic for nets subject to random noise in a static timing analysis of an initial integrated circuit (IC) design; calculating an upper bound for a delta delay of each net using the RNC statistic; identifying each net with a delta delay that exceeds the upper bound; identifying all nets including fan-in and fan-out cones connected to each net that exceeds the upper bound and performing a higher accuracy timing analysis for all nets that are marked. Using the upper bound for each delta delay of the nets subject to ransom noise, the delta delay of each net subject to a non-random noise, and the delta delay for all identified nets, to adjust the initial IC design, to close timing and generate a final IC design.

Abstract: A vehicle is configured to carry out external charging operation in which an in-vehicle battery is charged with electric power from a device outside the vehicle. The vehicle includes the in-vehicle battery, a charger and a control device. The charger is configured to output electric power from the device outside the vehicle to the in-vehicle battery. The control device is configured to control the charger so that the external charging operation is completed by time set by a user. Furthermore, the control device is configured to preferentially allocate a period of time during which the external charging operation is carried out in order of a priority time period set by the user, an immediate time period immediately after the priority time period and a preceding time period immediately before the priority time period.

Abstract: An electronic device is provided including: An electronic device comprising: a charging circuit including a battery coupled to a first end of an inductor, a first switch coupling a second end of the inductor to ground, and a second switch coupled to the second end of the inductor; and a controller configured to alternately close the first switch and the second switch in accordance with a duty cycle D, and increase a voltage transmitted to at least one system from the battery by using the inductor.

Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

Abstract: A method for automatically verifying validity of application of a refinement rule includes calculating a set of values that characterize a hierarchy of elements of the emulation. A currently calculated value for a first element at a first level of the hierarchy is compared with a previously calculated value that characterized the first element at a previous time. If the currently calculated value is the same as the previously calculated value, application of the refinement rule is determined to be valid for unnamed entities of the first element. If the currently calculated value is different from the previously calculated value, each currently calculated value that characterizes a lower level element at a lower level of the hierarchy is compared with a corresponding previously calculated value to identify a change and it is determined whether the change invalidates application of the refinement rule to an unnamed entity of the emulation.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and inserting a first plurality of scattering bars in the IC design layout to form a first circular pattern of scattering bars around the first main feature. The first main feature is positioned at a center portion of the first circular pattern of scattering bars.

Abstract: A method for debugging a system on chip (SoC) under test, the method may include executing a test code on the SoC, the test code designed to invoke a plurality of actions; recording output data from the SoC resulting from the executed test code; linking between actions detected in the recorded output data and actions of the plurality of actions of the test code by identifying a start and an end times of each of the detected actions in the recorded output data, and associating the identified start and end times with a start and an end times of actions of the plurality of actions of the test code; and causing display, via a graphical user interface, of a waveform representation of the detected actions over time, a representation of the test code and a representation of the output log.

Abstract: A method for charging rechargeable cells, in particular lithium ion cells. An apparatus for charging such cells. In order to specify a method for charging a lithium-based cell and an apparatus for charging a lithium-based cell, in which the capacitance of the cell is optimally used, the charging time is drastically shortened, the shelf life of the cell is extended and/or it is possible to increase the capacitance of the cell, a method is stated which includes the following steps, pulsed charging of the cell, wherein the charging current IL exceeds the nominal charging current ILmax of the cell during the charging pulses; and the cell is discharged between the charging pulses using load pulses.

Abstract: Disclosed are techniques for implementing electronic design layouts with symbolic representations. These techniques determine an abstraction scope of a layout circuit component in a layout of an electronic design by referencing a user input or one or more default settings of the abstraction mechanism and identify first data that are included in or associated with a schematic symbol for the layout circuit component by traversing data from a symbolic representation data source with reference to the abstraction scope with the layout editing mechanism. In addition, these techniques further generate a symbolic representation for the layout circuit component by reproducing at least some of the first data in the layout and perform one or more layout operations on the symbolic representation to improve the layout and to generate a result set for the one or more layout operations.

Abstract: This application discloses a computing system implementing tools and mechanisms to generate a framework for a system-level design of an electronic system, wherein the system-level design includes multiple electronic designs from different electronic design automation tools. The tools and mechanisms can correlate design components in the electronic designs to different portions of the framework for the system-level design, and determine whether the electronic designs are congruent with the system-level design based, at least in part, on the correlation of the electronic designs to the different portions of the framework for the system-level design.

Abstract: Provided is a renewable energy power generation system (10) having a renewable energy power generating apparatus (12) arranged to generate electric power; and a hydrogen power generation module (20) having a separation unit (22) adapted to separate water into hydrogen and oxygen, and a fuel cell unit (28) adapted to receive air or oxygen, and hydrogen from said separation unit or from a hydrogen storage; the fuel cell unit being arranged to produce electric power in the presence of hydrogen and oxygen; wherein the hydrogen power generation module being adapted to receive electric power from the at least one renewable energy power generating apparatus at least prior to production of electric power by the fuel cell unit.

Abstract: A wireless charging apparatus and a wireless charging method are provided. The method includes selecting at least one of a wireless power reception mode and a wireless power transmission mode by a wireless charging apparatus, wirelessly receiving electric power when the wireless power reception mode is selected, and wirelessly transmitting electric power when the wireless power transmission mode is selected.

Abstract: A graphical tool creates design-verification environments. The tool includes a graphical environment builder that allows for the drag and drop addition of verification IP (“VIP”) modules to a graphical verification environment. The tool assigns connector signals associated with source code that simulates a connection between a VIP module and the device under test (“DUT”). The tool learns which connection signals are suitable to connect a VIP to the DUT and facilitates selecting of the suitable signals in the environment development process. The tool converts the graphical environment to source code that can be executed to simulate testing on the DUT. The tool also allows a user to navigate between view modes that display the verification environment graphically, and that display the source code associated with components of the verification environment.

Abstract: This application discloses a computing system implementing tools and mechanisms to generate a framework for a system-level design of an electronic system, wherein the system-level design includes multiple electronic designs from different electronic design automation tools. The tools and mechanisms can correlate design components in the electronic designs to different portions of the framework for the system-level design, and determine whether the electronic designs are congruent with the system-level design based, at least in part, on the correlation of the electronic designs to the different portions of the framework for the system-level design.