Abstract: An circuit-component-migration-apparatus is a computer that performs migration of design data between different pieces of circuit design software. The circuit component migration apparatus may be a design apparatus in which circuit design software of a migration destination of design data operates. The circuit component migration apparatus includes a storage unit, an obtaining unit, and a control unit.

Abstract: A system-level simulation includes generating netlist information including component library information, which describes instances of the hardware components, and component instance information, which describes component dynamic libraries that include models of hardware components. The simulation is generated at simulation run-time based on the netlist information. Component dynamic libraries corresponding to the component library information are loaded based on the component library information. A simulation dynamic library referenced by the component dynamic libraries is loaded. One or more interlibrary adapters corresponding to the component dynamic libraries are loaded to provide compatibility between the component dynamic libraries and an application binary interface of the simulation dynamic library. Instances of hardware components are instantiated based on the component instance information, and the instantiated instances of the hardware components are connected to form the simulation.

Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted processor to generate an instruction set profile for each instruction of the instruction set architecture. A combination of instruction sequences for the targeted processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted processor. Performance of the targeted processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.

Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted processor to generate an instruction set profile for each instruction of the instruction set architecture. A combination of instruction sequences for the targeted processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted processor. Performance of the targeted processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.

Abstract: A method, executed by a computer, for routing a circuit includes receiving a logic structure for a circuit, retrieving a logic template, determining whether the logic structure for the circuit matches the logic template, and routing the circuit using a routing recipe corresponding to the logic template in response to determining that the logic structure matches the logic template. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method for determining the sensitivity of an analog output node of a mixed-signal module on a system on a chip (SoC) to noise coupling on the analog input nodes of the mixed-signal module includes (i) selecting an IP block for testing, (ii) selecting the output node, (iii) compiling a list of input nodes for testing, (iv) for each input node of the list, providing excitation signals at different frequencies, (v) for each provided excitation signal, determining the output node's noise sensitivity, and (vi) if any individual and/or cumulative noise sensitivity result exceeds a preset threshold, then modifying the SoC design to take corrective action.

Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.

Abstract: An electric motor drives a drive target and generates electricity. A charge-discharge control circuit controls charging and discharging of a power storage device. A controller controls a charge-discharge control circuit. The controller obtains a calculation value of an internal resistance of the power storage device based on a measured value of an open circuit voltage of the power storage device, and a measured value of an inter-terminal voltage and a measured value of a charge-discharge current when the power storage device is charged and discharged, and obtains a correction value of the internal resistance by correcting the calculation value of the internal resistance based on the measured value of the open circuit voltage.

Abstract: The present disclosure is directed to a system for battery management and protection. A battery protection circuit may include a power semiconductor switch and a control integrated circuit (IC). The battery protection circuit may be configured to regulate the charging and/or discharging of a battery and further prevent the battery from operating outside of a safe operating area based on a protection trip point (e.g. overcurrent detection point) of the protection IC. The protection IC may be configured to calibrate a protection trip point so as to compensate for process and temperature variations of on resistance (RSSon) of the power semiconductor switch.

Abstract: An apparatus is provided for wirelessly charging a mobile computing device and utilizing the mobile computing device as a power source. The apparatus includes: a first data and power interface; a second data and power interface; a wireless charging unit; and a control unit. The operation of the wireless charging unit and the control unit is configured to provide a first mode of operation of the apparatus when an external source connected to the apparatus via the second data and power interface is a load device in which power is delivered from the mobile computing device to the load device via the first and second data and power interfaces, and a second mode of operation of the apparatus in which power is delivered from a power receiver of the wireless charging unit to the mobile computing device via the first data and power interface.

Abstract: A method for calculating leakage of a circuit including a plurality of transistors includes simulating a three-dimensional model of the circuit, wherein the simulating accounts for a subset of the plurality of the transistors that includes less than all of the plurality of transistors, and calculating the leakage in accordance with the three-dimensional model.

Abstract: A battery state estimation system estimates a state of charge of a chargeable battery. A SOCv computing unit calculates a state of charge of the battery using a voltage applied across the battery. A SOCi computing unit integrates a current flowing through the battery to calculate a state of charge of the battery. A SOCw computing unit which performs weighted addition to the state of charge of the battery calculated by the SOCv computing unit and the state of charge of the battery calculated by the SOCi computing unit, wherein when the temperature of the battery is a threshold value or less and the current flowing through the battery is a threshold value or less, the SOCw computing unit sets the specific gravity at the state of charge of the battery calculated by the SOCi computing unit larger than that in other cases upon the weighted addition.

Abstract: A subthreshold standard cell library addresses the energy efficiency of electronic systems, thereby significantly reducing power consumption. Recent energy performance requirements are causing the next-generation system manufacturers to explore approaches to lower power consumption. Subthreshold operation has been examined and implemented in designing ultra-low power standard cell designs that operate beyond the normal modes of operation, with the potential for large energy savings. Operation of CMOS (Complementary Metal Oxide Semiconductor) transistors in the subthreshold regime, where the supply voltage used in operation is orders of magnitude below the normal operating voltage of typical transistors, has proven to be very beneficial for energy constrained systems as it enables minimum energy consumption in Application Specific Integrated Circuits (ASICs).

Abstract: A method, apparatus, and system are provided for monitoring environment parameters of critical facilities. A Remote Area Modular Monitoring (RAMM) apparatus is provided for monitoring environment parameters of critical facilities. The RAMM apparatus includes a battery power supply and a central processor. The RAMM apparatus includes a plurality of sensors monitoring the associated environment parameters and at least one communication module for transmitting one or more monitored environment parameters. The RAMM apparatus is powered by the battery power supply, controlled by the central processor operating a wireless sensor network (WSN) platform when the facility condition is disrupted. The RAMM apparatus includes a housing prepositioned at a strategic location, for example, where a dangerous build-up of contamination and radiation may preclude subsequent manned entrance and surveillance.

Abstract: A calculating part acquires a current position from an acquiring part. The calculating part searches for the position of a charging facility in charging facility information within a retaining part on the basis of the acquired current position, and specifies the charging facility for a next charging. The calculating part calculates a charging time based on a charged amount and a charging capacity of the specified charging facility. A selecting part selects peripheral facilities presented to a user based on calculated charging time and a standard time indicating an average time spent on using each peripheral facility registered in association with the specified charging facility retained in the retaining part, and displays the information regarding the selected peripheral facilities on the display part. Thus, assistance can be provided for the effective use of the time needed to charge a storage cell onboard a moving body at a charging facility.

Abstract: Provided is a logic configuration method for a semiconductor device having a plurality of memory units provided with a plurality of memory cells; each memory unit is configured to store truth table data in the memory cells thereof, the truth table data being for outputting a logic value in response to an address input, and to operate as a logic circuit; the memory units have n (where n is 2 or a higher integer) times two pairs of an input line and an output line; the n times two output lines from one memory unit among the memory units are connected to the n input lines of two other memory units; and the logic configuration method generates, on the basis of the circuit description describing the circuit configuration, a netlist having circuit connection information, extracts a logic cone from the netlist, and generates truth table data for the plurality of memory units, which constitute the logic cone, in the memory unit stage number corresponding to the number obtained by dividing the number of input lines to

Abstract: A layout design system includes a storage unit storing first and second standard cell designs, and a displacement module that arranges the first and second standard cell designs to generate an intermediate design in accordance with the chip design requirement. A first area for the first standard cell design and a second area for the second standard cell design are separated in the intermediate design by a filler design having no active area. Extended active areas are formed in the filler design in relation to the first standard cell design and second standard cell design.

Abstract: A wireless power transmission and charging system and method are provided. The wireless power may refer to energy that may be transferred from a wireless power transmitter to a wireless power receiver. The wireless power transmission and charging system may include a source device to wirelessly transmit power, and a target device to wirelessly receive power.

Abstract: A graphical tool creates design-verification environments. The tool includes a graphical environment builder that allows for the drag and drop addition of verification IP (“VIP”) modules to a graphical verification environment. The tool assigns connector signals associated with source code that simulates a connection between a VIP module and the device under test (“DUT”). The tool learns which connection signals are suitable to connect a VIP to the DUT and facilitates selecting of the suitable signals in the environment development process. The tool converts the graphical environment to source code that can be executed to simulate testing on the DUT. The tool also allows a user to navigate between view modes that display the verification environment graphically, and that display the source code associated with components of the verification environment.

Abstract: A graphical tool creates design-verification environments. The tool includes a graphical environment builder that allows for the drag and drop addition of verification IP (“VIP”) modules to a graphical verification environment. The tool assigns connector signals associated with source code that simulates a connection between a VIP module and the device under test (“DUT”). The tool learns which connection signals are suitable to connect a VIP to the DUT and facilitates selecting of the suitable signals in the environment development process. The tool converts the graphical environment to source code that can be executed to simulate testing on the DUT. The tool also allows a user to navigate between view modes that display the verification environment graphically, and that display the source code associated with components of the verification environment.