Abstract: A method of testing a circuit design includes generating, for each net of each critical path in the circuit design, a respective ring oscillator circuit design. The ring oscillator circuit design has a source gate coupled to a destination gate via the net and a feedback path that couples an output pin of the destination gate to an input pin of the source gate. Configuration data are generated to implement a respective ring oscillator circuit from each ring oscillator circuit design, and a programmable integrated circuit is configured with the configuration data. The method determines a delay of the net of each ring oscillator circuit.

Abstract: A graphical tool creates design-verification environments. The tool includes a graphical environment builder that allows for the drag and drop addition of verification IP (“VIP”) modules to a graphical verification environment. The tool assigns connector signals associated with source code that simulates a connection between a VIP module and the device under test (“DUT”). The tool learns which connection signals are suitable to connect a VIP to the DUT and facilitates selecting of the suitable signals in the environment development process. The tool converts the graphical environment to source code that can be executed to simulate testing on the DUT. The tool also allows a user to navigate between view modes that display the verification environment graphically, and that display the source code associated with components of the verification environment.

Abstract: A system and method for managing analog assertion publication and re-use for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to create, verify, formalize, and publish an analog assertion for a circuit design for subsequent re-use with another circuit design. Embodiments enable analog assertion handling while simultaneously depicting a circuit design in a schematic and/or layout editor window. Embodiments capture referenced circuit objects and parameterize the assertion for numerical values and connectivity. A designer may publish the assertion and annotate it with descriptive metadata, possibly with other assertions of related functionality, to a library accessible by users of analog design and verification tools.

Abstract: Techniques for compiling an integrated circuit (IC) design with an electronic design automation (EDA) tool are provided. The IC design may be compiled for different IC devices. When the IC design is compiled for a selected integrated circuit device, the EDA tool may analyze the IC design to determine whether the design is compatible with the selected IC device. If the IC design contains elements that are incompatible with the selected IC device, the EDA tool may compile the design based on a simulated removal of the incompatible elements. In some instances, the EDA tool may identify optimization opportunities in the IC design and may compile the design based on an optimized version of the IC design. The EDA tool may generate a compilation output (e.g., a performance analysis report) based on the simulated removal of the incompatible elements (or the optimized version of the IC design.

Abstract: Determining a circuit design-specific, failures in time rate for single event upsets for an integrated circuit (IC) includes determining, using a processor, a number of critical interconnect multiplexer bits for a circuit design for a target IC and determining a number of critical look-up table bits for the circuit design. Using the processor, a device vulnerability factor is estimated for the circuit design for the target IC using the number of critical interconnect multiplexer bits and the number of critical look-up table bits. The estimated device vulnerability factor can be stored, e.g., for subsequent comparison with other circuit designs.

Abstract: A charging device for use with an electric vehicle including a power storage device. The charging device includes a power conduit configured to electrically couple the power storage device to the charging device. The charging device includes a first protection device configured to electrically isolate the charging device from the power storage device if a current flowing through the power conduit exceeds a current limit. The charging device also includes a controller configured to control the current flowing through the power conduit if the current flowing through the power conduit causes an integration threshold to be exceeded, wherein the integration threshold is representative of a predetermined amount of current that is enabled to flow through the power conduit over a predetermined period of time.

Abstract: Dynamic yield prediction. In accordance with a first method embodiment of the present invention, a computer-implemented method includes collecting sample test information from a plurality of test-only structures prior to completion of the first wafer, gathering finished test data from all die of the first wafer, after completion of the first wafer, constructing a yield prediction model based on the sample test information and on the finished test data, and predicting, using the model, a percentage of die of the first wafer that will meet a particular specification. The method may further include a feedback loop to dynamically update the model.

Abstract: A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.

Abstract: A charging apparatus may include a power supply unit supplying charging power, a charging unit transferring the charging power from the power supply unit to an external charging target device, a charge controlling unit controlling a charging state of the charging unit, a display unit displaying the charging state according to controlling by the charge controlling unit and stopping a displaying operation when the charging target device is in a fully-charged state, and a delaying unit blocking a current supplied to the display unit and delaying the stopping of the displaying operation of the display unit for a preset time when the charging target device is recharged in the fully-charged state.

Abstract: Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description. The second function is determined to be a data consuming function of the first function. Within a circuit design, a port including a local memory is automatically generated. The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design.

Abstract: In accordance with an embodiment, a circuit includes a direct current (DC) output configured to be coupled to a rechargeable battery and a power factor corrector circuit coupled to the DC output, where the power factor corrector circuit includes a controller, and where the controller is configured to determine a switching frequency of the power factor corrector circuit in accordance with a battery charging curve of the rechargeable battery.

Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

Abstract: Disclosed is a wireless power transmitter that includes a resonator that provides charging electric power to a wireless power receiver and a metal layer spaced apart from the resonator by a preset interval, with a line width of the resonator being smaller than the preset interval between the resonator and the metal layer.

Abstract: A method of forming a semiconductor arrangement is provided. The semiconductor arrangement includes an interconnection arrangement comprising a first connection between a driver and a receiver. At least one buffer is disposed along the first connection to reduce delay associated with the interconnection arrangement. However, buffers increase power consumption, and thus a determination is made as to whether a buffer is unnecessary. A buffer is determined to be unnecessary where removal of the buffer does not violate a timing constraint regarding an amount of time a signal takes to go from the driver to the receiver. If a buffer is determined to be unnecessary, the buffer is removed to reduce power consumption.

Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.

Abstract: A method of designing an acoustic microwave filter comprises generating a proposed filter circuit design having an acoustic resonant element with a defined admittance value, introducing a lumped capacitive element in parallel and a lumped inductive element in series with the resonant element, selecting a first capacitance value for the capacitive element and a first inductance value for the inductive element, thereby creating a first temperature modeled filter circuit design, simulating the first temperature modeled filter circuit design at a first operating temperature, thereby generating a first frequency response, selecting a second capacitance value for the capacitive element and a second inductance value for the inductive element, thereby creating a second temperature modeled filter circuit design, simulating the second temperature modeled filter circuit design at a second operating temperature, thereby generating a second frequency response, and comparing the first and second frequency responses to the

Abstract: A method of automated optical inspection (AOI) for a plurality of unique semiconductor packages can comprise providing a plurality of semiconductor die formed as a reconstituted wafer. A plurality of unit specific patterns can be formed by forming a unit specific pattern over each of the plurality of semiconductor die, wherein each of the unit specific patterns is customized to fit its respective semiconductor die. A plurality of images can be acquired by acquiring an image for each of the plurality of unit specific patterns. A plurality of unique reference standards can be created by creating a unique reference standard for each of the plurality of unit specific patterns. Defects can be detected in the plurality of unit specific patterns by comparing one of the plurality of unique reference standards to a corresponding one of the plurality of images for each of the plurality of unit specific patterns.

Abstract: A battery pack including: a battery including a battery cell; a temperature sensor for detecting a temperature of the battery; a cell voltage measuring unit for measuring a cell voltage of the battery cell and generating cell voltage data including a cell voltage value; a temperature measuring unit coupled to the temperature sensor, the temperature measuring unit being for generating temperature data including a temperature value corresponding to the temperature of the battery detected by the temperature sensor; and a control unit for determining a maximum charging current value (MCCV) of a charging current for charging the battery based on the cell voltage data and the temperature data. The control unit is for transmitting the MCCV to a charging apparatus for supplying the charging current to the battery pack. The charging apparatus is for controlling the charging current supplied to the battery pack to have a value below the MCCV.

Abstract: Methods and systems for implementing repetitive track patterns for electronic designs are disclosed. The method determines a track pattern within a period and repeats the track pattern for a number of times to form repetitive track patterns. Compliance with photomask designation design rules and track pattern design rules by both the track pattern and the repetitive track patterns is maintained by adding one or more intermediate tracks. A track may be added or removed from the track pattern or replaced by another track associated with a different width by using one or more intermediate tracks. The method may validate a period and replace an invalid period with a valid period. During the identification of the tracks in a track pattern for constructing repetitive track patterns, the method also forward predicts a predetermined number of tracks or predicts one or more tracks for a predetermined distance.

Abstract: A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image.