Abstract: One aspect identifies an interconnect and associated design rule(s) and moves a portion of the interconnect to an adjacent track by using a spreading process on a one-dimensional design data based on the design rule(s) to determine whether the interconnect including the moved portion provides a DRC clean implementation. This aspect examines an interconnect in its entirety without being confined within a prescribed boundary of a fixed region in the layout. The one-dimensional design data provides expedient runtime and may be converted back into two-dimensional form for the layout. Another aspect iterates through multiple spreading distances to route or modify interconnects in a layout by performing multiple Boolean operations on the interconnect and adjacent shape(s) to determine the final form of the newly created or modified interconnect complying with various design rules.

Abstract: In some embodiments, in a method, cell layouts of a plurality of cells are received. For each cell, a respective constraint that affects a geometry of an interconnect to be coupled to an output pin of the cell in a design layout is determined based on a geometry of the output pin of the cell in the cell layout.

Abstract: A circuit providing voltage cell balancing is provided. The circuit includes a cell balancing network comprising separate switching circuits, each being configured to balance a respective cell voltage for a respective cell of a plurality of voltage cells based on a respective switching control signal. A control circuit includes a plurality of current sources, each of the plurality of current sources selectively connected to a respective one of the separate switching circuits to independently control operation of each of the separate switching circuits of the cell balancing network to balance the voltage across the plurality of voltage cells.

Abstract: A power adapter for mobile devices may include an alternating current to direct current (AC/DC) converter. The AC/DC converter may convert electric power from a power source. The power adapter may include a housing enclosing the AC/DC converter. The power adapter may include a power plug extending from the housing along a first axis. The power adapter may include a Universal Serial Bus (USB) plug extending from the housing along the first axis and on an opposite end of the housing from the power plug. The power adapter may include a device charging plug pivotally coupled to the housing.

Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.

Abstract: A system and method for modeling microelectromechanical devices is disclosed. An embodiment includes separating the microelectromechanical design into separate regions and modeling the separate regions separately. Parametric parameters or parametric equations may be utilized in the separate models. The separate models may be integrated into a MEMS device model. The MEMS device model may be tested and calibrated, and then may be used to model new designs for microelectromechanical devices.

Abstract: A method for calculating leakage of a circuit including a plurality of transistors includes simulating a three-dimensional model of the circuit, wherein the simulating accounts for a subset of the plurality of the transistors that includes less than all of the plurality of transistors, and calculating the leakage in accordance with the three-dimensional model.

Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.

Abstract: An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.

Abstract: One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions.

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for verifying an integrated circuit (IC) layout. In some cases, approaches include a computer-implemented method of verifying an IC layout, the method including: obtaining data about a process variation band for at least one physical feature in the IC layout; determining voltage-based process variation band thresholds for the at least one physical feature in the IC layout; determining whether the process variation band for the at least one physical feature in the IC layout meets design specifications for the IC layout based upon the voltage-based process variation band thresholds for the at least one physical feature in the IC layout; and modifying the IC layout in response to a determination that the process variation band for the at least one physical feature does not meet the design specifications.

Abstract: Systems, methods, and apparatus are disclosed for charging a vehicle in a wireless power transfer system. In one aspect, a method of charging a vehicle is provided, including determining distances between the vehicle and each of a plurality of charging stations. The method further includes selectively communicating, based on the distances, with a first charging station of the plurality of charging stations.

Abstract: Clock networks constructed with variable drive strength clock drivers are prepared for tuning. The clock drivers are built from a smaller set of base standard cells. Locations of the input and output netlists of the macrocells are marked and reserved even through the extraction process. The macrocells are able to be flattened, generating a netlist with the base cells, and recombined during circuit simulation, thereby reducing the number of iterations, making the tuning flow more efficient. The clock network is initially tuned by adding or removing cross-links in the mesh to balance capacitive loads on each driver of the clock mesh.

Abstract: A battery system comprising a battery management system (BMS) is disclosed. The BMS has a hierarchical structure including an upper layer master BMS and a lower layer slave BMS. The master transmits a request signal to the slave wirelessly, and the slave transmits a response signal based on the request signal wirelessly to the master.

Abstract: A wireless charging device of the disclosure is used for carrying out wireless battery charging for an electronic device. The wireless charging device includes a wireless charger, a positioning seat, and an adjusting seat. The positioning seat is fixed with the wireless charger. The positioning seat and the wireless charger collectively form a sliding space. The adjusting seat supports the electronic device. The adjusting seat extends into the sliding space and slides along the sliding space relatively to the positioning seat, to adjust a location of a transmitter coil center of the wireless charger, which results that the transmitter coil center of the transmitter of the wireless charger aligns to a receptor coil center of the electronic device.

Abstract: This disclosure is directed to a self-powered internal medical device. An example device may comprise at least an energy generation module and an operations module to at least control the energy generation module. The energy generation module may include a structure to capture certain molecules in the organic body based at least on size, the structure including a surface of the device in which at least one opening is formed. The at least one opening may be sized to only capture certain molecules. The operations module may initiate oxidation reactions in the captured molecules to generate current for device operation or for storage in an energy storage module. Thermoelectric generation circuitry in the energy generation module may also use heat from the reaction to generate a second current. The operations module may control operation of a sensor module and/or communication module in the device based on the generated energy.

Abstract: At least one example embodiment discloses a method of generating parameters of an amplifier. The method includes displaying, by a processor, a graphical user interface on a display, the graphical user interface associated with input and output parameters of the amplifier, receiving input parameter values for the amplifier, generating output parameter values for the amplifier based on the obtained input parameter values and displaying the generated output values on the display.

Abstract: A transistor model defines the carrier mobility as a combination of both drift-diffusion mobility and ballistic mobility. The ballistic mobility is calculated based on the assumption that the kinetic energy of carriers near an injection point is no greater than the potential energy difference of carriers near that injection point. The abruptness of the onset of velocity saturation, as well as the asymptotic velocity associated therewith is made dependent on the degree to which the velocity is ballistically limited. The model further takes into account the inertial effects on the velocity and/or charge flux associated with carriers. The model computes the mobility and hence the velocity of carriers in accordance with their positions in the channel both along the direction of the current flow as well as the direction perpendicular to the current flow.

Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.