Abstract: An analog circuit simulator includes a processor that is configured to search design data for analog circuits and an analog node connecting the analog circuits; collect variable information that concerns voltage and current variables and is related to input to and output from the analog node; convert the variable information into time functions; and compute the time functions upon each occurrence of a given event and execute simulation of the analog node.

Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

Abstract: A method for automatic design of an electronic circuit, includes: generating (100) a layout (L) of the aforesaid electronic circuit; generating (200) abstract data (A) at the substrate level associated to the layout (L) of the aforesaid electronic circuit; generating (300) a grid (TG) of subdivision into meshes and nodes with respect to a view pertaining to the aforesaid abstract (A) and applying it to the aforesaid substrate (SBS); and extracting (400), on the basis of the aforesaid subdivision grid (TG), a full electrical netlist (NC) pertaining to the substrate (SBS). The method further includes performing an evaluation (500, 600) of the interactions between devices (DV) of the electronic circuit at the substrate level according to the aforesaid full electrical netlist (NC) pertaining to the substrate (SBS).

Abstract: An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.

Abstract: A power converter circuit includes input terminals configured to receive an input voltage and an input current and output terminals configured to provide an output voltage and an output current. A boost converter stage is coupled between the input terminals and the output terminals. The power converter circuit is operable to operate in one of a first operation mode, a second operation mode, and a third operation mode dependent on the output voltage. The first, second and third operation modes are mutually different. In each of the first, second and third operation modes, the input current is controlled dependent on the input voltage.

Abstract: A cell phone charger that charges a cell phone and includes: prongs that are retractable and are plugged into an electrical outlet, a prong base that the prongs are assembled on, a rack gear that is connected to the prong base and has a rack gear hole, an extension gear that is engaged with the rack gear and is rotated to move the rack gear between a retracted position and an extended position, a spring that provides a force to place the rack gear and prongs is the retracted position, a retraction activator that controls a lock pin based on a retraction signal, a controller that generates the retraction signal and transmits the retraction signal to the retraction activator, and a voltage converter that converts provides a DC voltage and charges the cell phone.

Abstract: A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage.

Abstract: The disclosed embodiments comprise a multi-stage circuit operating across different power domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit integrated with a level shifter that transfers data across different power domains. The master and slave stages of the flip-flop may be split across two tiers of a 3D IC and may include (i) a level shifter across different power domain integrated within the flip-flop circuit, (ii) reduced one-state writing delays by a self-induced power collapsing technique, (iii) splitting flip-flop power supplies in different tiers using monolithic 3D IC technology, and (iv) cross power domain data transfer between 3D IC tiers.

Abstract: It is an object of the present invention to provide an image processing device for allowing an actual-image-closer pattern to be formed based on the design data, or its simulation image. In order to accomplish the above-described object, the proposal is made concerning an image processing device which includes an image processing unit which sets the operation condition of a charged-particle beam device on the basis of the design data on a semiconductor element. Here, the image processing device accesses a library for storing device-condition information on the charged-particle beam device, pattern types, and a plurality of combinations of pattern information on each pattern-region basis. Moreover, the image processing device forms a composite image of each pattern region, using the pattern information on each pattern-region basis, and based on the device-condition information and the selection of a pattern type from the pattern types.

Abstract: One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.

Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

Abstract: A technique generates small scale clock trees using a spine-based architecture (using spine routing) while also using clustered placement. Techniques are used to control clock sink cluster contents in order to minimize clock skew, minimize clock buffer count, and minimize use of routing resources. This approach also provides the user with ample structure and control to customize small efficient clock trees, and can also reduce clock power consumption.

Abstract: Reducing jitter in a circuit design includes selecting a plurality of circuit elements of a circuit design clocked using a first clock signal and assigning, using a processor, the plurality of circuit elements to different ones of a plurality of groups according to a balancing criterion. The circuit elements assigned to a first group of the plurality of groups are clocked using the first clock signal. The circuit elements assigned to a second group of the plurality of groups are clocked using a second clock signal different from the first clock signal.

Abstract: A system and method for enabling compatibility of wired charging with wireless charging are disclosed. The system includes an interface circuit, a wired charging unit and a wireless charging unit. The interface circuit is configured to connect the wired charging unit and the wireless charging unit to a power management unit; the wired charging unit is connected to the power management unit via an interface circuit and is configured to charge the power management unit by using a charging circuit in the power management unit; and the wireless charging unit is connected to the power management unit via the interface circuit and is configured to charge the power management unit by using the same charging circuit as that used by the wired charging unit.

Abstract: Systems and methods are provided for designing semiconductor device layouts. For example, an initial layout including multiple target features associated with semiconductor devices is received. One or more dummy features are determined to be inserted into the initial layout. The target features and the dummy features are assigned to multiple masks based at least in part on one or more mask-assignment rules. A final layout is generated for fabricating the semiconductor devices.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. The method may include providing, using a processor, a low-power electronic design and determining if a power domain associated with the low-power electronic design is active. The method may further include identifying, at a register transfer level (RTL) at least one X value associated with an active power domain wherein identifying occurs during a simulation.

Abstract: An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires.

Abstract: A system, method, and computer program product for automatically providing circuit designers with verification coverage information for analog/mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to assemble a schematic representation of a lower-level circuit design from pre-defined building blocks and various types of connections. Embodiments convert the schematic representation into a behavioral model for rapid simulation. Building blocks in the behavioral circuit have coverage-related terms defined either by the designer or by default, such as input and output value ranges, internal state changes, and state timers and timing-related constraints. Embodiments simulate the behavioral circuit, and determine and tangibly output coverage-related information. Manual and automatic behavioral circuit and stimulus modification can maximize coverage for improved behavioral circuit verification.

Abstract: A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image.

Abstract: A number of wafers of a semiconductor device are inspected to generate a plurality of wafer inspection data. A method for identifying critical hot spots to improve lithographic process of manufacturing the semiconductor device uses design signature analytics according to the plurality of wafer inspection data with reference to the design data of the semiconductor device. Design signature analytics includes global alignment, full chip pattern correlation, pattern characterization and design signature inference. The global alignment compensates for the physical coordinate offsets between the chip design data and the wafer inspection data. The full chip pattern correlation uses multi-stage pattern matching and grouping to identify highly repeating defects as hot spots. Pattern characterization extracts the design patterns and design signatures of the highly repeating defects.