Abstract: The controller (185) of a fuel cell stack (151) in a vehicle (150) responds to lower demand to cause a diverter (172) to direct all air from the cathodes (19) except as required to generate sufficient power to limit cell voltage to a safe idle voltage threshold, cause storage in an energy storage system (201) sufficient to limit cell voltage to the idle voltage threshold unless SOC is too high, connects a voltage limiting load (220) to the stack sized to consume all power not consumed by auxiliary BOP, or, for longer idles, air-starves the stack and powers BOP from storage. In response to increase in a demand signal, the controller causes flow of all air to the cathodes. In response to an off signal (223) or a start signal (193) the controller causes a shutdown routine or a startup routine in each of which all generated power is stored to maintain fuel cell voltage below a threshold, or is consumed in the voltage limiting load.

Abstract: A wireless power transmission and charging system and method are provided. The wireless power may refer to energy that may be transferred from a wireless power transmitter to a wireless power receiver. The wireless power transmission and charging system may include a source device to wirelessly transmit power, and a target device to wirelessly receive power.

Abstract: A system and method for modeling microelectromechanical devices is disclosed. An embodiment includes separating the microelectromechanical design into separate regions and modeling the separate regions separately. Parametric parameters or parametric equations may be utilized in the separate models. The separate models may be integrated into a MEMS device model. The MEMS device model may be tested and calibrated, and then may be used to model new designs for microelectromechanical devices.

Abstract: Systems and techniques for parallel battery balancing are described. A battery assembly comprises a first battery interface and a second battery interface; the first battery interface may connect to a first battery exhibiting a first voltage profile and the second battery interface may connect to a second battery exhibiting a second voltage profile. The battery assembly further comprises a current flow control mechanism to direct current flow to, from, and between the first battery and the second battery, with current directed to each battery being adapted so as to be compatible with the voltage profile of the battery.

Abstract: An electronic device may include an alternating current (AC) adapter to receive AC power and to provide a direct current (DC) voltage. The AC adapter may include a transistor and a capacitor. The capacitor to store a voltage based on the received AC power, and the transistor to remove a portion of the power stored in the capacitor based on the received AC power.

Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.

Abstract: A vehicle that is chargeable using power from an external power source includes: a chargeable electric storage device; a charging device that charges the electric storage device by using the power from the external power source; and a control device that, based on maximum supply power that is able to be supplied to the electric storage device and based on actual charge power actually supplied to the electric storage device, calculates a shortfall with respect to charge power supplied to the electric storage device in a case where charging is performed at the maximum supply power, and stores information relating to a causal factor for the shortfall.

Abstract: A portable device charger is disclosed, which is able to charge portable devices whether it is connected to an external power supply or not. The charger connects to household AC power as well as USB DC power, and further has a photovoltaic cell. It manages the input power from these three sources to charge a portable device and/or recharge the charger's battery, by supplementing the input power with battery power if the device demands more power than the input source, and charging the battery with remaining power if the device demands less power than is provided by the input source. The charger turns off the AC/DC converter and draws no power from the AC source if the battery is full and there is no attached device.

Abstract: Embodiments of a local interface unit are disclosed that may allow for managing credits and tokens as part of flow control method. The local interface unit may include a transmit unit and a receive unit. The transmit unit may be configured to receive credits and tokens, determine an available number of credits based on the number received tokens, determine an available number of tokens based on the number of received tokens, and send the available credits to an arbitration unit. The available credits may then be updated, by the transmit unit in response to receiving a selected transaction from the arbitration, and the transmit unit may then transmit the selected transaction, and update the available credits and the available tokens once the transaction has been sent. The receive unit may be configured to send credits and tokens to a transmit unit, and receive a transaction sent by a transmit unit.

Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.

Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.

Abstract: A communication system includes a first interface module which can be coupled to a first logic unit and a second interface module which can be coupled to a second logic unit. The first and second interface modules are interconnected by a virtual channel over a routing network. The first interface module is configured to receive messages from the first interface module and to send the received messages over the virtual channel to the second interface module. The second interface module is configured to transmit the received messages to the second logic unit. The second interface module is further configured to receive a processing complete signal from the second logic unit when the received messages have been processed in the second logic unit and is further configured to send an acknowledgement signal to the first interface module after reception of the processing complete signal. Further a communication method is provided.

Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.

Abstract: A self-charging electric bicycle that includes a solar panel disposed upon a back plate above the rear wheel, a first dynamo operationally engaged by the rotational force of the front wheel, a second dynamo operationally engaged by the rotational force of the rear wheel, and a third dynamo operationally engaged at a high gear ratio by a second chain in operational communication with the bicycle pedal crank, wherein an electric battery disposed within a housing upon the bicycle frame is charged and recharged when the bicycle is moved and pedaled and when sunlight is incident the solar panel, whereby an electric motor is activatable to drive the bicycle, as desired.

Abstract: A system and method for a universal battery charger is presented. An RFID tag on a battery-powered device communicates battery information to the charger to allow the charger to optimally charge the battery. The battery charger has a charging cord with a charge plug at an end of the cord to connect the charging cord to a port on a device. The charging cord contains an RFID antenna near the end of the cord. The RFID antenna has a limited reading range. When the charge plug is inserted into a charging port on a battery-powered device, an RFID reader uses the RFID antenna to read the information stored on the RFID tag. Based on the RFID tag information, a charging selector selects a current and voltage to be output to charge the device through the device port.

Abstract: A residential box data center system includes an information technology (IT) load, a direct current (DC) power generator electrically connected to the IT load and a housing, where both the IT load and the DC power generator are located in the housing.

Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.

Abstract: Test circuitry for characterizing manufacturing variations in semiconductor devices is provided. The test circuitry may include an array of devices under test and associated decoder circuitry for addressing the array of devices under test. In one arrangement, the test circuitry may be formed on a wafer at a scribe line located between adjacent integrated circuit dies on the wafer. In another arrangement, the test circuitry may be formed within an integrated circuit to provide on-chip variation monitoring capabilities. A measurement circuit may be used to gather test data from the array of devices under test and may be used to generate control signals that compensate for the manufacturing variations detected in the array of devices under test.

Abstract: This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.

Abstract: A first signal is transmitted through a first path. A computing device determines a signal propagation time of the first signal. The computing device transmits a second signal through a second path, wherein the second path includes the second signal traversing across at least one interconnecting structure. The computing device determines a signal propagation time of the second signal. The computing device determines a propagation time difference between the signal propagation time of the first signal and the signal propagation time of the second signal. The computing device adjusts a clock based on the determined propagation time difference.