Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.

Abstract: A charger in one aspect of the present invention includes: a connecting portion, two protection devices, a charging device, a control device, and a voltage detection device. A first protection device is configured such that its power consumption in a charging inhibited state is lower than that in a charging permitted state. A second protection device is configured such that its power consumption in the permitted state is lower than that in the inhibited state. The control device is configured to respectively set, when the battery is not connected to the connecting portion, the first protection device to the inhibited state and the second protection device to the permitted state, and thereafter switch, when the voltage value of the charging path detected by the voltage detection device is equal to or greater than a predetermined specified voltage value, the second protection device to the inhibited state.

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for aligning a set of orthogonal circuit elements in an integrated circuit (IC) layout. In some embodiments, a computer-implemented method for aligning a set of orthogonal circuit elements in an IC layout includes: classifying each orthogonal circuit element in the set of orthogonal circuit elements as including a first space-designated edge and a second space-designated edge; and aligning each orthogonal circuit element on an edge placement grid according to the first space-designated edge and the second space-designated edge, the edge placement grid having a first set of space-designated grid lines separated by a first distance, and a second set of space-designated grid lines separated by a second distance, wherein the first set of space-designated grid lines is separated from the second set of space-designated grid lines by an offset distance.

Abstract: A core circuit that can be connected in a hierarchical manner, and configured to test a multiple circuits is disclosed. The core circuit includes at least one real input for receiving scan-in data for controlling operation of the core circuit. The core circuit further includes an input register coupled to the at least one real input and configured to store data. The core circuit further includes at least one scan chain coupled a subset if registers of the register chain and configured to generate scan-out data representing the presence of faults in an circuit. Furthermore, the core circuit includes at least one control pseudo-output coupled to the input register and configured to route at least a subset of the data to another register chain in the core circuit or to another core circuit.

Abstract: Apparatus for charging an electrical energy store from an AC voltage source. The apparatus includes a rectifier device with a capacitor interconnected in parallel with the rectifier device A current controller device is interconnected with the rectifier device. A converter device is interconnected with the current controller device. The converter device includes at least one first half-bridge having two switches connected in series, An inductor is interconnected with a connection point of the switches of the first half-bridge Depending on the voltage of the AC voltage source and a current through the inductor a switch of the current controller device and one of the switches of the first half-bridge of the converter device are switchable by means of a controller in such a manner that a current for charging the electrical energy store drawn from the AC voltage source and a voltage of the AC voltage source are substantially in phase.

Abstract: A method and apparatus are provided for implementing enhanced physical design quality using historical placement analytics in a design of an integrated gate. Mathematical data analysis is performed to determine placement trends in order to seed an initial placement of subsequent physical design placement processes. A placement seed is generated for a subsequent placement process.

Abstract: A method and apparatus are provided for implementing enhanced physical design quality using historical placement analytics in a design of an integrated gate. Mathematical data analysis is performed to determine placement trends in order to seed an initial placement of subsequent physical design placement processes. A placement seed is generated for a subsequent placement process.

Abstract: A method 100, a computer program product and a system of checking an integrated circuit layout for instances of a reference pattern is provided The method 100 comprises the steps of: i) receiving 102 the integrated circuit layout, ii) receiving 104 a drawing of the reference pattern from a user, iii) deducting 106 a basic pattern definition from the drawn reference pattern, iv) determining 108 a set of topological relation based on the drawn reference pattern, v) forming 110 a complex pattern description which is a combination of the deducted basic pattern definition and the set of topological relations, vi) checking 112 the integrated circuit layout for patterns that match the complex pattern description to find instances of the reference pattern in the integrated circuit layout, and vii) storing 114 found instances of the reference pattern.

Abstract: A vehicle is disclosed that includes a battery and a controller programmed to calculate a battery voltage characteristic from previously measured charge and discharge data. The battery voltage characteristic is based on differences between the previously measured values when state of charge falls in a range in which the differences are approximately equal. Outside of the range, the charge and discharge voltage data are corrected based on a square root of time to obtain the battery voltage characteristic. The characterization may be performed with a high-rate continuous charge and discharge cycle. Also disclosed is an apparatus for generating the battery characteristic that includes a bi-directional power supply. The battery voltage characteristic is obtained based on the differences of the charge and discharge voltage data and corrected data based on the square root of time. A method is also disclosed based on the same.

Abstract: In accordance with an embodiment, an electronic device includes a controller configured to be coupled to a first switch of a power factor corrector. The controller is configured to produce a variable switching frequency depending on a load current. For a first load current, the controller is configured to produce a first switching frequency, and for a second load current, the controller is configured to produce a second switching frequency.

Abstract: Via redundancy insertion is described. A via layout is analyzed by identifying each via, and for each via, identifying a location therefore in the layout, whether the via is redundant and a layout configuration for the via. Each via is classified into a bin of similar layout configurations. For each bin of redundant vias, possible via replacement candidates are determined from a database of possible replacement vias, and the candidates are ranked according to rule-based, recommendation-based and/or model-based criteria. For each via in each bin having a replacement(s), an optimal replacement is identified from among the ranked candidates taken in ranked order that first satisfies another criteria, such as not violating an applicable design rule. The layout is then updated with the optimal replacement.

Abstract: A method for charging a battery, including: determining a final state of charge and a final temperature of the battery; and calculating charging power and/or cooling power required to reach the two final values within a minimum amount of time.

Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.

Abstract: Embodiments include systems and methods for implementing a dummy fill flow in a processor design that points to a library of fill shapes that are associated with (e.g., defined and supported according to) a particular foundry process. For example, a set of cell types is generated in accordance with a foundry process definition, so that each unit cell type has a unique type identifier and an associated polygon definition. These cell types can be stored as a cell library. An automated fill flow can generate a dummy fill of an integrated circuit geometry with respective shape fills having shape cells that each point to one of the cell types in the cell library. Some implementations can use the cell library to stream in and instantiate the fill in the geometric design of the integrated circuit.

Abstract: A method for mapping an element of an engineering schematic into a schematic element database is provided. The method electronically scans a schematic to recognize a plurality of elements visually represented in the schematic, wherein each of the plurality of elements is associated with predefined schematic element visual attributes; and maps each of the plurality of recognized elements to any one of a plurality of saved database elements, based on common visual attributes.

Abstract: An active balancing and battery charging system for a battery including a plurality of packs made up of cells. An H-bridge circuit having a nominal system voltage as an input generates a square wave output to a plurality of step-down transformers each associated with a pack, where the plurality of step-down transformers provide an active balancing voltage of about the nominal pack voltage. Each pack may include a balancing transformer including a common primary coil receiving the active balancing voltage from the associated step-down transformer or the pack itself. The balancing transformer also includes a plurality of secondary coils each associated with the respective plurality of cells of the pack. A voltage induced in the secondary coils causes a discrete charge current to flow to any cells in the pack that are undercharged relative to other cells.

Abstract: A scatterometry target formed relative to an elevationally outermost surface of a substrate includes features having an optical property that is different from that of spaces between the features. The substrate has spaced-apart parallel elongated blocking lines having an optical property different from that of spaces between the blocking lines. The blocking lines are elevationally inward of the target features. The target features and the blocking lines overlap within a same vertical region of the substrate. Polarized electromagnetic radiation having multiple wavelengths is impinged onto the scatterometry target. Pitch of the blocking lines is less than the smallest wavelength of the impinged radiation. The blocking lines reduce spectrum variation to below a detectable level for any polarized electromagnetic radiation passing to elevationally inward of the blocking lines.

Abstract: A method for programming a cluster-based field programmable gate array (FPGA) device includes providing a netlist and cluster size information, translating the netlist into a hypergraph, partitioning the hypergraph into multiple partitions and optimizing the Rent characteristic, translating the partitions into clusters, placing the clusters on the FPGA device, routing interconnects using a pre-fabricated routing resource on the FPGA device, generating a programming bitstream in response to the placing and routing, and providing the programming bitstream to the FPGA device to realize the user design.

Abstract: One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions.

Abstract: A solar electric system comprises photovoltaic elements having integrated energy storage and control, ideally on each PV-panel. The energy storage media may be primary or secondary cylindrical cells interconnected into a battery and/or an array of capacitors (or super-capacitors) and are accompanied by an electronic control circuit which may perform a variety of functions, including but not limited to: power quality control, load following, pulse powering, active line transient suppression, local sensing, remote reporting, wireless or wired communications allowing two way programmable control through local or remote operation. The operation of the system may yield direct current or with the integration of bidirectional micro-inverters create distributed alternating current generation enhanced with energy storage and control two way energy flows between the solar system and the grid.