Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.

Abstract: An integrated circuit (IC) design is received. The IC design has devices on different layers electrically connected to each other by conductive vias extending between the different layers. Relative locations of the vias, and of conductive components of the devices within adjacent layers of the different layers, are identified. The conductive components that overlap redundant vias are also identified. This allows 2D via checker data, that is a combination of the 3D adjacent layers, to be generated. The 2D via checker data includes rectangular geometric shapes that represent each instance of the conductive components overlapping redundant vias. Thus, the 2D via checker data is output, and lack of rectangular geometric shapes in the 2D via checker data provides data of locations in the IC design that fail to have redundant vias.

Abstract: Integrated circuit design computing equipment may perform register moves within a circuit design. When moving the registers, counter values may be maintained for non-justifiable elements. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that is used to generate a sequence for resetting the circuit design. The adjustment value may be bound by a user-specified maximum value. The user-specified maximum value may constrain logic/physical synthesis transforms and local/global retiming operations. If the counter value for a non-justifiable element is equal to the user-specified maximum value, then all future forward retiming across that element is prevented. If the maximum counter value is less than the user-specified maximum value, the user may optionally shorten the reset sequence.

Abstract: An IC includes a first IC portion and a second IC portion. The IC includes a first set of standard cells in the first IC portion. The IC includes a plurality of memory cells and a second set of standard cells in the second IC portion. The second set of standard cells is located in channels between the memory cells. The IC further includes a plurality of GDHS cells in the first IC portion. The GDHS cells are configured to switch power on and to switch power off to the first set of standard cells. The IC further includes a plurality of CHS cells in the first IC portion. The CHS cells are configured to switch power on and to switch power off to the second set of standard cells in the second IC portion.

Abstract: A simulation apparatus has: a first processing part configured to obtain a value of a parameter in a first set relating to the forming of the pattern; a second processing part configured to obtain a value of a parameter in a second set that is at least partially same as the parameter in the first set and relating to the forming of the pattern; and an integration processing part configured to evaluate, based on the value of the parameter in the first set and the value of the parameter in the second set, a state of the pattern formed on the substrate and a forming condition when the pattern is formed, and to determine based on the result of the evaluation whether or not to make at least one of the first processing part and the second processing part recalculate the value of the parameter in the corresponding set.

Abstract: A method of designing an acoustic microwave filter comprises generating a proposed filter circuit design having an acoustic resonant element with a defined admittance value, introducing a lumped capacitive element in parallel and a lumped inductive element in series with the resonant element, selecting a first capacitance value for the capacitive element and a first inductance value for the inductive element, thereby creating a first temperature modeled filter circuit design, simulating the first temperature modeled filter circuit design at a first operating temperature, thereby generating a first frequency response, selecting a second capacitance value for the capacitive element and a second inductance value for the inductive element, thereby creating a second temperature modeled filter circuit design, simulating the second temperature modeled filter circuit design at a second operating temperature, thereby generating a second frequency response, and comparing the first and second frequency responses to the

Abstract: Some embodiments determine a merged timing graph for a multi-instance module (MIM), wherein each node in the merged timing graph corresponds to a pin in the MIM, and wherein each node in the merged timing graph stores timing information associated with the corresponding pins in multiple instances of the MIM in a circuit design. The embodiments can then determine an ECO for the MIM based on the merged timing graph.

Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

Abstract: A method includes identifying a first set of a first care area with a first sensitivity threshold, the first care area associated with a first design of interest within a block of repeating cells in design data; identifying an additional set of an additional care area with an additional sensitivity threshold, the additional care area associated with an additional design of interest within the block of repeating cells in design data; identifying one or more defects within the first set of the first care areas in one or more images of a selected region of a sample based on the first sensitivity threshold; and identifying one or more defects within the additional set of the additional care areas in the one or more images of the selected region of the sample based on the additional sensitivity threshold.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing virtual prototyping for electronic designs. These techniques identify a plurality of leaf cells into a hierarchical physical design of an electronic design, generate the hierarchical physical design at least by performing hierarchical placement for the plurality of leaf cells based in part or in whole upon one or more factors, and revise the placed hierarchical physical design at least by performing hierarchical routing for the plurality of leaf cells on the hierarchical physical design. One aspect may further detach a virtual cell in the hierarchical physical design at least by grouping a first set of leaf cells and representing the first set of leaf cells with a first placeholder.

Abstract: A system-level simulation includes generating netlist information including component library information, which describes instances of the hardware components, and component instance information, which describes component dynamic libraries that include models of hardware components. The simulation is generated at simulation run-time based on the netlist information. Component dynamic libraries corresponding to the component library information are loaded based on the component library information. A simulation dynamic library referenced by the component dynamic libraries is loaded. One or more interlibrary adapters corresponding to the component dynamic libraries are loaded to provide compatibility between the component dynamic libraries and an application binary interface of the simulation dynamic library. Instances of hardware components are instantiated based on the component instance information, and the instantiated instances of the hardware components are connected to form the simulation.

Abstract: A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells assigned to a plurality of cell groups. The method may further include obtaining, from a user, a selection of a user-defined criterion and a selected cell group from the plurality of cell groups. The method may further include partitioning the selected cell group into a first partitioned cell group including a first subset of the plurality of cells and a second partitioned cell group comprising a second subset of the plurality of cells. The method may further include generating a floorplan comprising the first partitioned cell group and the second partitioned cell group.

Abstract: Methods and systems for timing analysis and optimization of asynchronous circuit designs are disclosed. Registration stages are placed between combinational logic circuits. For timing purposes, the registration stages are modified to have a duplicate set of pins. New paths are formed in the circuit for the purposes of timing analysis. The paths are analyzable by timing tools. Once the timing analysis is complete, the paths are reverted to original paths, and new devices are selected for the circuit design based on results of the timing analysis. An updated design is sent for manufacture, based on the timing analysis and optimization of the asynchronous circuit.

Abstract: A specification editing unit edits a hardware specification file in order to replace a plurality of arrays used in a plurality of processes with a shared array. If a post-edit hardware specification file does not satisfy constraint, a specification transforming unit transforms the hardware specification file so that the plurality of processes are executed in a parallel manner. An architecture generating unit generates an architecture file expressing an architecture of an SoC (System On Chip) having hardware corresponding to the hardware specification file.

Abstract: A method for designing an integrated circuit die, the method including generating a first layout for the die which includes at least one decap; and performing a post-processing decap insertion operation to add at least one additional decap in excess of the at least one decap, the operation including: for at least a portion of the first layout, identifying at least some of whichever locations in at least the portion have positive slack, as “candidate” locations; and inserting at least one additional decap at at least one respective location from among the “candidate” locations.

Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include storing one or more electronic circuit designs at an electronic circuit design database and receiving a user input associated with one of the electronic circuit designs. Embodiments may include scanning the one or more stored electronic circuit designs and generating a network including a relationship graph and a component map, based upon, at least in part, the scanning Embodiments may include generating at least one next neighbor component based upon, at least in part, the network and the received user input. Embodiments may include displaying one or more user-selectable options at a graphical user interface, wherein the user-selectable options include the at least one next neighbor component.

Abstract: A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.

Abstract: The multi-functional charger includes a charger body, circuit board and an external charging plug, wherein the circuit board is arranged in the charger body and electrically connected with the external charging plug; the external charging plug is detachably connected with one end of the charger body and electrically connected with the circuit board through a connecting cable; a containing cavity is formed in the charger body and used for containing the connecting cable; the charger body is further provided with at least one mounting groove, the interiors of all the mounting grooves are respectively and detachably, connected with a functional assembly, and each functional assembly are in electric connection with the circuit board; the functional assembly includes a retractable USB assembly for the cable connection and a charging power assembly for electric energy storage.

Abstract: A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.

Abstract: A wireless charging apparatus and a wireless charging method are provided. The method includes selecting at least one of a wireless power reception mode and a wireless power transmission mode by a wireless charging apparatus, wirelessly receiving electric power when the wireless power reception mode is selected, and wirelessly transmitting electric power when the wireless power transmission mode is selected.