Abstract: The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in the same horizontal or vertical region, to give the user an intuitive view of time going left to right or top to bottom.

Abstract: A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.

Abstract: A method for combining verification data may include using a processor, obtaining verification data and a verification model from each of a plurality of verification engines relating to different verification methods, the verification data relating to a plurality of verification tests that were conducted on a design under test (DUT) using the plurality of verification engines; using a processor, merging the verification models obtained from the plurality of verification engines into a merged verification model; using a processor, calculating a combined verification metric grade for a plurality of verification entities in the merged verification model using verification metric grades for each of the plurality of verification entities calculated from the verification data obtained from the plurality of engines and applying a combined verification metric grade rule; and outputting the combined verification metric grade via an output device.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information. The electronic design may be further updated based in part or in whole upon results of performing one or more analyses on the extracted view.

Abstract: A mobile body is driven by power that is wirelessly transferred from a non-contact power supply device including a power transmission resonator that transmits power in accordance with a non-contact power supply method. The mobile body includes a power reception resonator, a power storage, a motor, a controller, and at least two wheels driven independently of each other by the motor, the at least two wheels including a first movement axis and a second movement axis with an axial orientation different from that of the first movement axis, and moving the mobile body along the first movement axis and the second movement axis. When the mobile body moves to a power supply target range, the controller controls the motor based on power reception status information indicating a status of power reception by the power reception resonator, and moves in a flat plane direction.

Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.

Abstract: A direct charging method is provided that alerts a mobile device when a switching power converter is operating in a constant-current mode to alert the mobile device of an output current without the use of a secondary-side current sense resistor.

Abstract: An emulator emulating a DUT emulates a clock generator for generating clock signals of the DUT with jitter. As part of generating clock signals, the emulator generates a jitter clock value for each clock signal. To generate a jitter clock value for a clock signal, the emulator identifies a clock parameter stored for the clock signal and sums the clock parameter with a jitter value randomly selected from the jitter range of the clock signal. When a system fast clock cycle starts, the emulator determines the lowest value from the generated jitter clock values. The emulator outputs an edge on clock signal having the lowest jitter clock value. The emulator generates a new jitter clock value for each clock signal and the process repeats during the next system fast clock cycle.

Abstract: A simulation method for a mixed-signal circuit system includes: detecting a plurality of registers and a clock signal included in the mixed-signal circuit system; performing a timing analysis converting operation upon a circuit block coupled between any two register of the plurality of registers to obtain a converted circuit system; and performing a Static Timing Analysis operation upon the converted circuit system; wherein when the circuit block is convertible into a combinational circuit block, the timing analysis converting operation includes: converting the circuit block to the combinational circuit block, wherein the combinational circuit block is logic gate-level.

Abstract: An optical proximity correction method, comprising: dissecting an edge of a design pattern (120/220) to form a segment (Seg1/Seg2); setting target points of the segments (Seg1/Seg2), and if the segments (Seg1/Seg2) translate in a direction vertical to the segments (Seg1/Seg2), controlling tangent points (P1/P2) of the segments (Seg1/Seg2) tangent to a simulated pattern (110/210) to coincide with the target points; computing edge position differences of the target points; and correcting the design pattern (120/220) according to the edge position differences.

Abstract: A rechargeable battery pack including at least one interface for establishing a mechanical and/or electrical connection of the rechargeable battery pack to a hand-held power tool and/or a charging device. The interface includes contact elements for the electrical and/or mechanical contacting of corresponding contact elements on the hand-held power tool and/or corresponding contact elements on the charging device, at least one contact element being a signal contact element electrically connected to a coding element. The rechargeable battery pack also includes a rechargeable battery pack electronics system configured for providing information regarding the rechargeable battery pack via the signal contact element, and storing at least in part in the coding element, and a microcontroller connected to the rechargeable battery pack electronics system in such a way that the microcontroller detects when information is called up at the signal contact element by a hand-held power tool and/or by a charging device.

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes forming a first partition by selecting at least one in-boundary PG cell from the group of PG cells, adding at least one out-boundary PG cell from the group of PG cells into the first partition, forming a second partition by selecting the remaining in-boundary PG cells and the remaining out-boundary PG cells in the group of PG cells, calculating the total area of the in-boundary PG cells in the first partition, calculating the total area of the out-boundary PG cells in the first partition, calculating the total area of the in-boundary PG cells in the second partition, calculating the total area of the out-boundary PG cells in the second partition, and calculating the difference between the total areas of in-boundary PG cells in the first partition and the out-boundary PG cells in the first partition.

Abstract: A computer executing method is provided in this disclosure. The computer executing method is configured for synthesizing a clock tree circuit, the clock tree circuit includes a plurality of clock pins, a plurality of weight values are set between any of the clock pins, the computer executing method includes steps of: establishing a graph model; utilizing a force directed algorithm to calculate a branch position according to the weight values and a position of the clock pins; setting a guide buffer in the branch position and updating a netlist; performing a clock tree synthesis (CTS) and executing a post-CTS static timing analysis (STA); determining whether an analysis result of the post-CTS STA and a timing setup value is identical or not; and if the analysis result does not match the timing setup value, re-establishing a graph model.

Abstract: A method for generating a validation test, may include obtaining, using a processor, a validated scenario for generating a test for a verification model, the validated scenario represented in the form of a directed acyclic graph with a plurality of actions as nodes of the graph. The method may also include analyzing, using the processor, the graph to identify an action of said plurality of actions designed to be executed on a thread that is associated with a faulty scheduler of a verification model to be tested. The method may further include, upon identifying the identified action, amending, using the processor, the verified scenario by removing the identified action from the graph.

Abstract: Disclosed are techniques for processing layout designs based on dynamically-generated lithographic models. Lithographic models are determined for a plurality of regions of a reticle prior to lithographic simulation. During lithographic simulation, lithographic models for a small area within a particular region are generated based on the lithographic models for the particular region, the lithographic models for one or more neighboring regions, and location information of the small area relative to the region and to the one or more neighboring regions. The lithography models comprise illuminating and imaging system models and mask electro-magnetic field models.

Abstract: A method for increasing the decoupling capacitance in a microelectronic circuit. The method comprises producing a circuit design of the microelectronic circuit, analyzing the produced circuit design, and subsequently filling gaps in the circuit design by cells with decoupling capacitor.

Abstract: A power device, system and method. The device may include a housing defining a first support operable to support a first battery pack, and a second support operable to support a second battery pack; a circuit selectively electrically connecting the first battery pack and the second battery pack in series, the circuit including an output terminal to provide an output voltage to a powered device, a first bypass portion operable to selectively electrically disconnect the first battery pack from the circuit, and a second bypass portion operable to selectively electrically disconnect the second battery pack from the circuit; and a boost converter electrically connected to the circuit and operable to boost a voltage at the output terminal.

Abstract: A virtual force controlled collapse chip connection (C4) pad placement optimization frame-work for 2D power delivery grids is proposed. The present optimization framework regards power pads as mobile “positive charged particles” and current resources as a “negative charged back-ground.” The virtual electrostatic force is calculated from voltage gradients. This optimization framework optimizes pad locations by moving pads according to the virtual forces exerted on them by other pads and current sources in the system. Within this framework, three algorithms are proposed to meet various requirements of optimization quality and speed. These algorithms minimize resistive voltage drop (IR drop), the maximum current density, and power distribution network metal power dissipation at the same time.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing a schematic circuit design component as a transmission line model in a schematic driven extracted view for an electronic design. These techniques identify a schematic circuit component design form a schematic design of an electronic design and identify or determine layout device information of a layout circuit component design corresponding to the schematic circuit component design. An extracted view may be generated or identified for the electronic design at least by using a transmission line model based in part or in whole upon connectivity information or a hierarchical structure of the electronic design. The electronic design may then be modified or updated based in part or in whole upon results of performing one or more analyses on the extracted view with the transmission line model.

Abstract: A power storage system or a power storage device that can restore reduced capacity is provided. The power storage device includes a first exterior body, a first electrode, a second electrode, a first electrolyte solution, and a carrier ion permeable film. The first electrode, the second electrode, and the first electrolyte solution are covered with the first exterior body. The first electrode and the second electrode are in contact with the first electrolyte solution. The first electrolyte solution includes carrier ions. A first opening is provided in the first exterior body. The carrier ion permeable film is provided to be in contact with the first electrolyte solution and so as to block the first opening without any space. The carrier ion permeable film is configured to be impermeable to water and air but permeable to the carrier ions.