Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.

Abstract: Provided is a method for simulating a semiconductor device. The method includes extracting a Hamiltonian and an overlap matrix of a semiconductor device using a density functional theory or a tight-binding method, calculating each of Bloch states for each corresponding energy, obtaining a first reduced Hamiltonian and a first reduced overlap matrix with a reduced matrix size, and calculating a final transformation matrix and a final energy band structure in which all of unphysical branches, wherein the semiconductor device includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the channel region includes unit cells, each of which includes different material or has different structure.

Abstract: A main board for a computer device can include main board components arranged on a first surface of the main board and Trusted Platform Module (TPM) components arranged on the first surface of the main board. The TPM components can be located in a predetermined area of the main board that is detachable from the main board (e.g. by means of a predetermined break line). A method for producing an embodiment of the main board with an integrated TPM can include producing a Printed Circuit Board (PCB); arranging a plurality of main board components in a first area of the PCB; and arranging TPM components in a second area of the PCB that is a detachable predetermined area of the main board. A predetermined breakline which at least partly surrounds the predetermined area can be formed by drilling holes to form a perforated line.

Abstract: Disclosed is a method and apparatus that takes timing information associated with a plurality of inputs to a cell, such as an AND-gate, within an integrated circuit (IC) design, store the timing information in a timing information register (TIR) associated with an index identifying the source of the timing information and track the source of the timing information for a predetermined number of cells through the index. The timing information in the TIRs is merged upon the index indicating that the timing information has been tracked through a predetermined number of cells.

Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.

Abstract: Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.

Abstract: An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).

Abstract: An electronic device includes an interface unit that receives power from an external device, a charging unit that charges a battery with power received from the external device via the interface unit, and a control unit that stops operations of units excluding the interface unit and the charging unit, when the charging unit charges the battery with the power received from the external device via the interface unit and a predetermined function is selected.

Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

Abstract: Systems and methods for validation of photonics device layout designs. A method includes receiving, by a computer system, a rule deck and a layout design. The layout design includes silicon photonics (SiP) structures. The method includes performing a verification process to produce verification results. The verification results include violations and the violations include SiP violations. The method includes performing SiP spacing filtering to filter the SiP violations into true SiP violations and false SiP violations. The method includes storing the true SiP violations in a result database.

Abstract: Systems and methods for producing individualized processing chips, each individualized processing chip being arranged to carry out a common processing operation are disclosed. A processing chip design is received, wherein the common processing operation is specified, at least in part, by the processing chip design. For each individualized processing chip the processing chip design is individualized to produce an individualized processing chip design, in accordance with an individualized set of transformations for the individualized processing chip, by including a respective set of modifications as part of the individualized processing chip design that implement the individualized set of transformations. Each transformation of the individualized set of transformations is a transform for an interconnect, specified in the processing chip design, of at least two logic cells specified in the processing chip design.

Abstract: The present disclosure provides a method for modeling, including: S1): designing a test key having a source, a drain, and a gate, and testing the test key to obtain test data; S2): extracting a model parameter according to the test data; S3): verifying reasonableness of a physical characteristic of the model parameter based on a relationship between a source-drain voltage and a drain current, if the reasonableness passes the verification, a model file is established and the method proceeds to S4), if the reasonableness fails the verification, the method returns to S2) to adjust the model parameter, until the reasonableness passes the verification; S4): performing quality assurance on the model file, if the model file passes the quality assurance, the modeling is completed, if the model file fails the quality assurance, the method returns to S2) to adjust the model parameter until the model file passes the quality assurance.

Abstract: One embodiment of the present disclosure provides a system for determining a hybrid-manufacturing plan for manufacturing an integrated circuit (IC). During operation, the system can obtain a set of hybrid-manufacturing constraints for manufacturing the IC. The set of hybrid-manufacturing constraints can include a set of primitives, a set of atoms, and an atom end-state vector. An atom can correspond to a unit of spatial volume of the IC. A primitive can represent an additive, subtractive, or a mixed manufacturing process corresponding to one or more atoms of the IC. Next, the system can determine a plurality of feasible hybrid-manufacturing plans based on the set of manufacturing constraints. Each feasible hybrid-manufacturing plan can represent an ordering of the set of primitives that satisfies the atom end-state vector. The system can then determine costs for manufacturing the IC using the plurality feasible hybrid-manufacturing plans.

Abstract: A formal verification EDA application can be configured to receive a circuit design of an IC chip. The circuit design of the IC chip comprises a set of properties for the IC chip and constraints for the IC chip. The formal verification EDA application generates an array of CNF files based on the circuit design of the IC chip. Each CNF file can include a Boolean expression that characterizes a selected property of the set of properties and data fields characterizing initial states for literals in the Boolean expression and the constraints of the IC chip. The formal verification application can also be configured to output the array of CNF files to a hardware prototyping platform. The hardware prototyping platform can be configured to execute a hardware instantiated SAT solver for the Boolean expression in each CNF file in the array of CNF files.

Abstract: Systems and method are provided that include a standard cell with multiple input and output storage elements, such as flip flops, latches, etc., with some combination logic interconnected between them. In embodiments, the slave latches on input flip flops are replaced with a fewer number latches at a downstream node(s) of the combination logic resulting in improved performance, area and power, while maintaining functionality at the interface pins of the standard cell. The process of inferring such a standard cell from a behavioral description, such as RTL, of a design or remapping equivalent sub-circuits from a netlist to such a standard cell is also described.

Abstract: A design method of a semiconductor integrated circuit according to embodiments includes: creating pseudo-cell information for cells included in cell library information, the pseudo-cell information reflecting the degree of difficulty of pin access that connects wires to pins set in the cells; and using cells with a low difficulty of pin access with reference to the pseudo-cell information in timing optimization.

Abstract: A method to provide an automated circuit design tool that mitigates or overcomes the inefficiencies present in the prior art tools ensuring a more efficient use of computer resources and a reduction in the time taken to design a suitable circuit that meets the design specification is presented. The computer-implemented method of designing a circuit configuration of a circuit, has the following steps 1) providing a first set of circuit configurations comprising one or more circuit configurations, 2) simulating each, circuit configuration of the first set of circuit configurations. In addition, the steps include: 3) scoring each, circuit configuration of the first set of circuit configurations based on a design specification and the simulation, or simulations, of step 2), and 4) providing a second set of circuit configurations comprising one or more circuit configurations that are dependent on the scores as determined in step 3).

Abstract: Training data may be collected for each design intent in a set of design intents by identifying a set of failures that is expected to occur when the design intent is manufactured, and recording a failure mode and a location of each failure in the set of failures. Next, the training data may be used to train a machine learning model, e.g., an artificial neural network, to predict failure modes and locations of failures. The trained machine learning model, e.g., trained artificial neural network, can then be used to predict a set of failures for a given design intent. Next, for each predicted failure, a reticle enhancement technique (RET) recipe may be selected based on the failure mode of the failure, and the selected RET recipe may be applied to an area around the location of the failure.

Abstract: The disclosure provides a design method for paralleled SiC power switching devices based on wiring optimization which belongs to the field of power electronics technology, aiming at the problem that in the existing scheme of paralleled SiC devices, the optimal performance of SiC devices cannot be presented with paralleled multiple SiC devices due to limitations of the unequal switching losses and transient currents. The design method comprises at least three wiring separation slots being arranged in parallel and in sequence on a PCB circuit board; wherein a power half-bridge composed of two SiC devices is arranged in each wiring separation slot, thereby increasing a parasitic inductance between adjacent power half-bridges. The disclosure can improve the current sharing performance of the switching transient current existing in the application of multiple paralleled SiC devices, so that SiC devices can be applied to high-power and high-current power electronic converters stably and reliably.

Abstract: A layout routing structure and a layout routing method for improving an SI performance of a signal are provided. Each of two positive and negative differential traces on a PCB includes multiple segments D1, multiple segments D2 and multiple segments D3. In each of the two differential traces, the segment D1 and the segment D2 are staggered and parallel to each other, the segment D2 is routed between any two segments D1, and any two adjacent segments D1 and D2 are connected by the segment D3. In one of the two differential traces, all of the segments D1 are routed on the glass cloth, and all of the segments D2 are routed on the epoxy resin. In the other of the two differential traces, all of the segments D1 are routed on the epoxy resin, and all of the segments D2 are routed on the glass cloth.