Abstract: An apparatus, a recording medium, and a method for generating a control parameter of a screen printer are disclosed. The apparatus includes a memory that stores a simulation model configured to derive predictive inspection information on a printed state of solder paste based on a plurality of control parameters of the screen printer; a communication circuit configured to receive first inspection information on a plurality of solder pastes printed by the screen printer based on a first control parameter, and a processor electrically connected to the memory and the communication circuit.

Abstract: A method of determining a failure model of a resist process of a patterning process. The method includes obtaining (i) measured data of a pattern failure (e.g., failure rate) related to a feature printed on a substrate based on a range of values of dose, and (ii) image intensity values for the feature via simulating a process model using the range of the dose values; and determining, via fitting the measured data of the pattern failure to a product of the dose values and the image intensity values, a failure model to model a stochastic behavior of spatial fluctuations in the resist and optionally predict failure of the feature (e.g., hole closing).

Abstract: A charging load detection circuit includes a charging circuit, a frequency generation unit, and a control unit. The control unit controls the frequency generation unit to generate a pulse voltage with a fixed first frequency and a fixed first amplitude, and the frequency generation unit provides the pulse voltage to an output terminal of the charging circuit. The control unit detects whether a load is coupled to the output terminal by detecting whether the first frequency and the first amplitude are varied, and controls connecting or disconnecting a charging path of the charging circuit according to whether the load is coupled to the output terminal.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: A method of reconstructing an emulated circuit layout for graphical display includes receiving a pre-layout circuit including one or more devices and one or more nodes. The method includes generating a Detailed Standard Parasitic Format (DPSF) netlist representing a post-layout circuit. The DPSF netlist includes a plurality of instances representing the one or more devices, the one or more nodes, and one or more parasitic elements not included in the pre-layout circuit. The method includes identifying at least one node of the one or more nodes that is associated with the one or more parasitic elements. The method includes updating the DPSF netlist to associate the one or more parasitic elements with the at least one node. The method includes constructing graphical representation of the post-layout circuit based on the updated DPSF netlist. The method includes causing a display device to display the graphical representation.

Abstract: A signal integrity simulation method for an encryption hybrid model is provided. A step response data of a SPICE model is extracted through a transient simulation. An external random code signal is generated. The extracted step response data is imported as an input source for an ADS channel simulator. An eye diagram at a RX end is calculated by the ADS channel simulator based on an algorithm and the external random code signal, to perform measurement on the eye diagram. With the signal integrity simulation method for an encryption hybrid model such as an IBIS AMI model, the problem that signal integration simulation cannot be accurately performed or cannot be performed because models provided by the manufacturer are encrypted or the types of models provided by the manufacturer are not consistent can be effectively solved.

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

Abstract: An analog circuit netlist translation system is disclosed. The analog circuit netlist translation system comprises a model translation module configured to receive an analog circuit netlist; and transform the analog circuit netlist into a digital model. In some embodiments, the digital model comprises a set of zero-delay loops. The analog circuit netlist translation system further comprises a translation methodology module configured to determine a set of closed loop values respectively associated with the set of zero-delay loops, in order to eliminate the set of zero-delay loops within the digital model. In some embodiments, the set of closed loop values are determined by the translation methodology module in a single timeslot.

Abstract: A system and a method are disclosed for placing hardware components on a printed circuit board (“PCB”) in a way that enables all hardware components on the PCB to be passively cooled without using active cooling systems. Components are selected to be placed onto the PCB and heat metrics for each component is obtained (e.g., from a server). The components are ranked based on the amount of heat that each component generates. A corresponding position for each of the hardware components is determined based on the ranking of the components and the orientation of the PCB. The placement is based on the concept that air having higher temperature rises while air having cooler temperature falls. A representation of the PCB according to corresponding positions of the hardware components may be generated for display.

Abstract: High-level synthesis implementation of data structures in hardware can include detecting, within a design and using computer hardware, a data structure and a compiler directive for the data structure. The design may be specified in a high-level programming language. Using the computer hardware and based on the compiler directive, a modified version of the design may be created by, at least in part, generating a modified version of the data structure based on the compiler directive. Using the computer hardware, a circuit design may be generated from the modified version of the design by creating, at least in part, a hardware memory architecture for the circuit design and mapping the modified version of the data structure onto the hardware memory architecture.

Abstract: A disclosed circuit prototyping system includes a hardware interface module configured for electronically connecting to a physical electronic device, a virtual circuit design interface to construct a virtual circuit for a plurality of virtual circuit devices including a virtual counterpart of the physical electronic device, and a circuit simulator configured to simulate the virtual circuit including communicating data with the physical electronic device by way of communication with the hardware interface module.

Abstract: Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.

Abstract: A method of enhancing a layout pattern includes determining a target layout pattern comprising a disk shape pattern associated with an opening. The method includes defining a polygon having a plurality of vertices on the disk shape pattern. The plurality of vertices coincide with a boundary of the disk shape pattern and the polygon is an initial layout pattern of the opening. The method includes performing an iterative correction of the initial layout pattern. The iterative correction includes projecting the layout pattern of the opening onto a substrate, determining an error between the target layout pattern and the projected layout pattern, and adjusting the layout pattern by moving the vertices of the polygon to generate a next iteration of the layout pattern. The method includes continuing the adjusting, projecting, and determining until a criterion is satisfied and a final iteration of the layout pattern of the opening is generated.

Abstract: An integrated circuit (IC) design comprising a scan chain may be received, where stimulus values may be scanned-in and response values may be scanned-out through a scan path in the scan chain, where the scan path may include a first scan cell and a second scan cell such that the first scan cell is downstream with respect to the second scan cell. The scan chain may be modified to enable observation of a 0 and a 1 value in the first scan cell in presence of a defect in the second scan cell, or observation of a 0 and a 1 value in the second scan cell in presence of a defect in the first scan cell.

Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop, a first inverter, and a second inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The second inverter is coupled to the first inverter, is configured to receive the second clock signal, and is configured to generate a third clock signal inverted from the second clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of the electronic design and receiving a selection of a subcircuit at a first position of the graphical user interface. In response to a user input, embodiments may include transitioning the subcircuit from the first position to a second position of the graphical user interface and determining one or more direct and indirect connections resulting from a potential placement at the second position. Embodiments may include determining an influence metric by applying an optimized connectivity rules definition upon the potential placement at the second position and the one or more direct and indirect connections. Embodiments may also include displaying feedback at the graphical user interface based upon, at least in part, the influence metric.

Abstract: A method of generating a layout design of an integrated circuit. The method includes forming a first region having at least two first-type cell rows extending in a first direction. Each one of the first-type cell rows has a first row height measured along a second direction perpendicular to the first direction. The method also includes forming a second region having at least two second-type cell rows extending in the first direction. Each one of the second-type cell rows has a second row height measured along the second direction. The first region is adjacent to the second region, and the first row height of the first-type cell rows is different from the second row height of the second-type cell rows.

Abstract: Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

Abstract: Various embodiments provide for testing a transmitter with interpolation, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer over a plurality of different interpolation phase positions of a phase interpolator; and using a pattern checker to error check the sampled data over the plurality of different interpolation phase positions to determine whether the data transmission test passes.

Abstract: A semiconductor device fabrication method includes providing a layout; performing an optical proximity correction on the layout to generate a corrected layout; and forming a photoresist pattern on a substrate by using a photomask fabricated with the corrected layout. The OPC may include: extracting edges of a pattern, the edges including a first edge and a second edge that converge to define a corner; generating a thin mask image by applying a thin mask approximation to the pattern; changing the first edge and the second edge into a first stepped edge and a second stepped edge; and applying a three-dimensional filter to the first and second stepped edges to generate an optical image including the corrected layout of the pattern to which the 3D filter is applied from the thin mask image.