Abstract: Techniques and systems for automatic net grouping and routing are described. Some embodiments can determine a set of net groups by automatically grouping nets that have (1) a same pin count, (2) a pin direction type that is in a predefined set of pin direction types, and (3) a pin order type that is in a predefined set of pin order types. Next, the embodiments can generate routing guidance by performing trunk planning for each net group. The embodiments can then perform detailed routing for each net in each net group by using the routing guidance.

Abstract: A method for generating redundant configuration in FPGA devices includes: analysing the configuration pertaining to a given design to be configured, or already configured, in the FPGA device, in order to identify programmed and empty configuration memory portions, configuring the FPGA device for implementing said design, measuring the power consumption of the configured FPGA device, copying the configuration from at least some subsets of the programmed portion to subsets of the empty portion, (a) verifying the configuration read back from said subsets of the empty portion with the configuration data read from said subsets of the programmed portion, (b) verifying whether the functionality of the design after the copy is still correct, (c) measuring the power consumption of the FPGA device, and verifying whether the power consumption of the FPGA device after the copy is acceptable according to pre-defined criteria, if the verification steps (a), (b) and (c) are all successful the redundant configuration is corr

Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.

Abstract: Methods, systems and computer program products for providing flexible constraint-based logic cell placement are provided. Aspects include determining a cell placement restriction rule that specifies an offset requirement between a first type of logic cell and a second type of logic cell. Responsive to placing a first cell that is the first type of logic cell within a semiconductor layout, aspects include tagging the first cell with the cell placement restriction rule. Aspects also include placing a second cell that is the second type of logic cell at an initial position within the semiconductor layout. Responsive to determining that the initial position of the second cell violates the cell placement restriction rule, aspects include repositioning the first cell or the second cell to a modified position within the semiconductor layout such that the modified position satisfies the cell placement restriction rule.

Abstract: A method includes obtaining a layout of a circuit pattern implemented on a semiconductor wafer, and identifying one or more polygons in the layout based on a length criteria. One or more measurement gauges are placed on the identified polygons to thereby obtain measured polygons. A scanning electron microscope (SEM) image of the circuit pattern is obtained. The SEM image is aligned with the layout including the measured polygons. A critical dimension of one or more objects in the SEM image is measured. The one or more objects correspond to the one or more polygons. Based on the measured critical dimension, it is determined whether the circuit pattern is acceptable.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: A power device including a housing, charging circuitry, and discharge circuitry. The housing defining a first support operable to support a first battery pack, and a second support operable to support a second battery pack. The charging circuitry electrically is connected to the first battery pack and the second battery pack in a parallel-type connection. The charging circuitry is configured to simultaneously charge the first battery pack and the second battery pack. The discharge circuitry is electrically connected to the first battery pack and the second battery pack.

Abstract: A method for controlling a processing apparatus used in a semiconductor manufacturing process to form a structure on a substrate, the method including: obtaining a relationship between a geometric parameter of the structure and a performance characteristic of a device including the structure; and determining a process setting for the processing apparatus associated with a location on the substrate, wherein the process setting is at least partially based on an expected value of the geometric parameter of the structure when using the processing setting, a desired performance characteristic of the device and an expected physical yield margin or defect yield margin associated with the location on the substrate.

Abstract: Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.

Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.

Abstract: A method and system for improving the performance of a computer in identifying and mitigating electromigration violations of a semiconductor device. A set of library gates is obtained and parasitic layout extraction is performed for each gate in the set of library gates to generate an extracted netlist. One or more passes of an electromigration analysis of the extracted netlist are performed to characterize each gate over a set of input parameters and to generate a maximum slew rate (MAX_SLEW) table and a maximum capacitance (MAX_CAP) table.

Abstract: A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions.

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

Abstract: A method for performing power mesh optimization with the aid of additional wires and an associated apparatus are provided. The method includes: reading a clock cell definition file to obtain respective basic information of a plurality of clock cells in a circuit design; and according to the respective basic information of the plurality of clock cells, executing a power mesh optimization procedure, including: regarding any type of clock cells in multiple types of clock cells within the plurality of clock cells, classifying the clock cells into a plurality of sub-types according to respective sizes of the type of clock cells; and performing power mesh enhancement on respective clock cells of a set of sub-types within the plurality of sub-types, to add a set of additional wires crossing a set of original wires in an original power mesh at each clock cell of any sub-type of the set of sub-types.

Abstract: Methods, systems and computer program products for avoiding Boolean DRC failures during cell placement are provided. Aspects include generating a semiconductor layout by filling a plurality of rows within a macro block with cells including functional cells and fill cells. Aspects also include modifying the semiconductor layout by removing one or more fill cells from the macro block to create a gap. Aspects also include examining a set of cells that border edges of the gap to identify one or more predicted rule violations. Based on the identified one or more predicted rule violations, aspects also include modifying the semiconductor layout to change a shape of the gap to avoid the one or more predicted rule violations.

Abstract: A system and method for input-directed constrained random simulation includes obtaining an initial state for a finite state machine (FSM) that models an electronic circuit design under test (DUT), the initial state assigning values to registers of the device under test, by providing an initial state function I(s) relating to the FSM to a satisfiability problem (SAT) solver to obtain register values that satisfy the initial state function. A random Boolean circuit R(i) is constructed. A SAT solver is queried for a satisfying assignment for a conjoined expression providing the conjunction of at least a valid-transition Boolean circuit T(s, i, s?) and the random Boolean circuit R(i), the valid-transition Boolean circuit describing valid transitions of the FSM as a function of current state s, inputs i, and next state s?. The satisfying assignment is added to the end of a constructed trace.

Abstract: Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for automatic test-pattern generation (ATPG) validation. An embodiment includes parsing an ATPG input, semantically analyzing the ATPG input, generating a first HDL model based on the semantic analysis, creating an HDL testbench based on the first HDL model, simulating an ATE test of a circuit structure, and outputting a validation result of the circuit structure, based on the simulating. In some embodiments, the parsing may include lexical and/or syntactic analysis. The HDL model may represent the circuit structure as functionally equivalent to the ATPG input, as determined based on the semantic analysis. In some embodiments, the ATPG input includes a cycle-based test pattern for a first block of the ATPG input, and the HDL testbench includes event-based test patterns that mimic given ATE behavior. The HDL model may be smaller in size than the ATPG input.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay optimization and methods of manufacture. The method includes performing, by a computing device, an exposure with a correction parameter to a first wafer; performing, by the computing device, a decorrection of the correction parameter; collecting, by the computing device, overlay data in response to the exposure and the decorrection; estimating, by the computing device, an optimal parameter from the overlay data; and applying, by the computing device, the optimal parameter to a second wafer to align an overlay in the second wafer.

Abstract: Superconducting circuit with virtual timing elements and related methods are described. A method includes specifying a superconducting circuit portion including a timing path comprising: (1) at least one logic gate to be implemented using Josephson junctions, (2) a first virtual timing element for defining a synchronization point along the timing path, and (3) a second virtual timing element for adding latency to the timing path. The method further includes synthesizing the superconducting circuit portion, where the synthesizing comprises treating the first virtual timing element as a first flip-flop and the second virtual timing element as a second flip-flop, where the first flip-flop is treated as being fixed in relation to the at least one logic gate along the timing path, but the second flip-flop is treated as being movable in relation to the at least one logic gate along the timing path.

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs.