Abstract: In accordance with some embodiments of the disclosure, an array substrate and a related liquid crystal display device are provided. The array substrate can include a plurality of pixel electrodes arranged on a base substrate, and a conductive opaque line arranged between two neighboring pixel electrodes and overlapping with each of the two neighboring pixel electrodes along a width direction of the conductive opaque line.

Abstract: A display device includes a substrate that includes a display area and a peripheral area that surrounds the display area; a display element disposed in the display area and that includes a pixel electrode, an emission layer, and an opposite electrode; a thin-film encapsulation layer that covers the display element and includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer; and at least one groove formed in the peripheral area, wherein at least a portion of the thin-film encapsulation layer fills the at least one groove, wherein the at least one groove is concave into a multi-layer structure that includes a first layer and a second layer disposed on the first layer, and the at least one groove has an undercut structure in which the second layer protrudes toward a center of the at least one groove.

Abstract: An array substrate and a method of fabricating the same are described. The array substrate has an active area and a winding area, wherein the array substrate has a base substrate, an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, a third metal layer, a patterned flat layer, a pixel defining layer, and a support layer. The first metal layer has at least one first wiring pattern. The second metal layer has at least one second wiring pattern. The third metal layer has at least one third wiring pattern. The pixel defining layer together with the support layer within the winding area have at least one undercut structure. The array substrate and the method of fabricating the same can reduce a width of a boundary formed by the winding area.

Abstract: The present invention is equipped with a substrate upon which a drive circuit containing a TFT, a planarization film, and an OLED are formed. The TFT is provided with a gate electrode, a drain electrode, a source electrode, and a semiconductor layer with regions serving as the channel and extends along a prescribed direction. The drain electrode and the source electrode are disposed such that respective portions of the drain electrode and the source electrode are arranged in an alternating manner along the prescribed direction. The connection between the drive circuit and the OLED is achieved via a conductor layer with a Ti layer and a Cu layer (Cu alloy layer) and is embedded in the interior of a contact hole formed in the planarization film, and the surface of the planarization film is formed with an arithmetic mean roughness Ra of no more than 50 nm.

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes a plurality of integrated circuits, a first encapsulant, a first redistribution structure, a plurality of conductive pillars, a second redistribution structure, a second encapsulant and a third redistribution structure. The first encapsulant encapsulates the integrated circuits. The first redistribution structure is disposed over the first encapsulant and electrically connected to the integrated circuits. The conductive pillars are disposed over the first redistribution structure. The conductive pillars are disposed between and electrically connected to the first and second redistribution structures. The second encapsulant encapsulates the conductive pillars and is disposed between the first redistribution structure and second redistribution structure.

Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a top surface. A conductive pad is over the top surface. An upper passivation layer is over the top surface and the conductive pad and includes a first implanted region. A polymer layer is over the upper passivation layer and the conductive pad. A conductive via penetrates through the upper passivation layer and the polymer layer, and electrically coupled to the conductive pad. A method for manufacturing a semiconductor structure is also provided.

Abstract: Provided are a display panel and a display device. In a repeating unit of the display panel, two first sub-pixels and two second sub-pixels form an arrangement with two rows and two columns, a row direction and a column direction of the arrangement are parallel to a row direction and a column direction of a matrix respectively, and two sub-pixels in a same row or a same column emit light of different colors. Outer edges of the two first sub-pixels and the two second sub-pixels are located on a same first virtual rectangle, and geometric centers of the two first sub-pixels and the two second sub-pixels form a first virtual parallelogram. Geometric centers of four third sub-pixels form a second virtual rectangle, and one side of the second virtual rectangle is parallel to the row direction or the column direction of the matrix.

Abstract: An OLED substrate is provided, which comprises a light emitting region and a transparent region, wherein the OLED substrate comprises a substrate and a display layer on the substrate, and a portion of the display layer located in the transparent region has a first hollow part. A method for manufacturing an OLED substrate and a transparent display comprising an OLED substrate are further provided.

Abstract: Provided are a flexible electronic device including device units, a first etching preventing layer provided on the device units, a conductive line provided on the first etching preventing layer and electrically connected to the device units, a flexible substrate covering the conductive line on the first etching preventing layer and the conductive line, a trench separating the device units and exposing a portion of a bottom surface of the first etching preventing layer and a side surface of each of the device units, and a flexible protective layer conformally covering a bottom surface of each of the device units and an inside of the trench, wherein each of the device units includes a protective substrate, driving parts provided on the protective substrate, and a first encapsulation layer configured to cover the driving parts, and a manufacturing method thereof.

Abstract: A display device includes: a substrate including a display area at which a pixel including a light emitting element is located and a peripheral area surrounding the display area; and a common voltage line on the substrate, the common voltage line configured to provide a common voltage to the pixel, the common voltage line including: a peripheral common voltage line on the peripheral area of the substrate to surround the display area and connected to a common electrode of the light emitting element; and a plurality of display common voltage lines crossing the display area and each contacting different portions of the peripheral common voltage line, the display common voltage lines being spaced apart from the common electrode of the light emitting element.

Abstract: A TFT array substrate and a method for manufacturing the same and an OLED display panel are provided. The method for manufacturing the TFT array substrate uses a mask to form an active pattern, a gate, a first electrode, a via and an opening in an interlayer dielectric layer and a gate insulating layer, a source, a drain, an opening in a planarization layer, and a spacer, respectively. The number of required masks is small and the processes are simple, which effectively improves the production efficiency and reduces the product cost.

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

Abstract: The present disclosure discloses a display screen, which includes an array layer, a planarization layer, a pixel defining layer, a support layer, and a buffer layer. The planarization layer is located on a surface of the array layer. The pixel defining layer is located on a surface of the planarization layer away from the array layer, and the support layer is located on a surface of the pixel defining layer away from the planarization layer. The buffer layer is located on at least one of an end surface of the support layer away from the pixel defining layer and an end surface of the support layer adjacent to the pixel defining layer.

Abstract: Disclosed is a display device including: a first conductive film over and in contact with a substrate; a first undercoat and a second undercoat over and in contact with the first conductive film; a pixel over the first undercoat; a wiring over the first undercoat, the first conductive film, and the second undercoat and in contact with the first conductive film between the first undercoat and the second undercoat. The first undercoat and the second undercoat are spaced from each other over the first conductive film and each cover a part of the first conductive film. The wiring is configured to form a terminal to which a signal for driving the pixel is input over the second undercoat.

Abstract: Provided are a display module and an electronic device. The display module includes an array substrate and an encapsulation layer disposed opposite to the array substrate, and the encapsulation layer includes an auxiliary electrode layer and a first electrical connector between the encapsulation layer and the array substrate; wherein the first electrical connector is used to support the encapsulation layer and is electrically connected to the auxiliary electrode layer and the cathode layer.

Abstract: A semiconductor device that includes a semiconductor layer disposed on a semiconductor substrate, a first semiconductor region provided in an upper layer portion of the semiconductor layer, a second semiconductor region provided in an upper layer portion of the first semiconductor region, a gate insulation film, a gate electrode, a first main electrode that is provided on an interlayer insulation film that covers the gate electrode and that is electrically connected to the second semiconductor region via a contact hole, and a second main electrode disposed on a second main surface of the semiconductor substrate. The first main electrode includes an underlying electrode film connected to the second semiconductor region via the contact hole, and a copper film provided on the underlying electrode film. The copper film includes at least a portion that serves as a stress relaxation layer having a smaller grain size than the other portion of the copper film.

Abstract: A semiconductor device comprises conductive lines, a conductive landing pad in electrical communication with a conductive line of the conductive lines, and a conductive interconnect structure in electrical communication with the conductive landing pad. The conductive interconnect structure comprises a contact plug in electrical communication with the conductive landing pad, and a global interconnect contact in electrical communication with the contact plug and having a greater lateral width than the contact plug. Related electronic systems and method are also disclosed.

Abstract: A semiconductor package includes a frame having a cavity and having a wiring structure connecting first and second surfaces opposing each other; a connection structure disposed on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a semiconductor chip disposed in the cavity and having a connection pad connected to the first redistribution layer; an encapsulant encapsulating the semiconductor chip; and a second redistribution layer having a redistribution pattern and a connection via connecting the wiring structure and the redistribution pattern. The connection via includes a first via connected to the wiring structure and a second via disposed on the first via and connected to the redistribution pattern, a lower surface of the second via has an area larger than an area of an upper surface of the first via.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes pixel circuits arranged in a matrix, and a blocking unit. Each pixel circuit includes: a driving transistor; a first switch transistor; a second switch transistor; and a third switch transistor. The blocking unit is configured to receive a fixed potential signal, and at least a partial area of the blocking unit is located between a first semiconductor connection portion and a second semiconductor connection portion, the first semiconductor connection portion is connected between a second electrode of the first switch transistor and a gate electrode of the driving transistor, and the second semiconductor connection portion is electrically connected between a first electrode of the second switch transistor and a data line.

Abstract: A display apparatus is provided, including a panel including a substrate including a display area where pixels are disposed, and a pad area where a terminal portion connected to the display area is disposed, and an insulating layer disposed over a same layer as in the display area and the pad area. A thickness of the insulating layer in the display area and a thickness of the insulating layer in the pad area are of different thicknesses.