Abstract: An organic light emitting diode display is described which includes a substrate having a display area and a non-display area; a metal layer disposed on the non-display area of the substrate, an insulating layer, a voltage line disposed on the gate insulating layer and receiving a driving voltage, a second voltage line disposed on the gate insulating layer and receiving a low driving voltage, an organic insulating layer, and a cathode electrode disposed on the organic insulating layer. The second voltage line and the cathode electrode are electrically connected to each other through an opening formed in the organic insulating layer, and the first voltage line or the second voltage line is electrically connected to the metal layer through an opening formed in the gate insulating layer.

Abstract: A low cost capacitor (e.g., metal-insulator-metal (MIM) capacitor) is included in the back-end-of-line layers for effective routing and area savings. The capacitor has a first electrode (e.g., a first terminal of the capacitor) including a conductive back-end-of-line (BEOL) layer and a second electrode (e.g., a second terminal of the capacitor) including a nitride-based metal. The capacitor also has an etch stop layer (e.g., a dielectric of the capacitor) between the first electrode and the second electrode.

Abstract: A semiconductor device includes an active region in a substrate. The active region extends in a first direction. The semiconductor device further includes a gate structure extending in a second direction different from the first direction. The gate structure extends across the active region. The semiconductor device further includes a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure. A first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width.

Abstract: A display device including a display panel including a display substrate having a display area and a pad area around the display area, and a plurality of signal wirings disposed in the pad area of the display substrate, a base film attached to the pad area of the display substrate, a plurality of lead wirings disposed on the base film and connected to the plurality of signal wirings, and a first curable pattern disposed between adjacent ones of the lead wirings, in which a surface height of the first curable pattern from a surface of the base film is less than a surface height of the lead wirings from the surface of the base film.

Abstract: A device is disclosed. In an embodiment the device includes an anode, an organic active layer above the anode, an organic layer sequence above the organic active layer, a metallic layer above the organic layer sequence and a cathode above the metallic layer, wherein the metallic layer includes Yb.

Abstract: A wafer structure, a method for manufacturing the wafer structure, and a chip structure. A front surface of a first chip provided with a photosensitive array is bonded to a front surface of a second chip provided with a logic device. An electrical-connection through-hole is provided on a back surface of the first chip at a pad region. The electrical-connection through-hole runs from the back surface of the first chip, via a top wiring layer in the first chip, to a top wiring layer in the second chip. A pad is provided on the electrical-connection through-hole. Hence, integration of a photosensitive device of a stacked type is achieved. There are advantages of a high integration degree and a simple structure. Transmission efficiency of a device is effectively improved, and complexity of a manufacturing process is reduced.

Abstract: Electronic device and associated methods with multiple well areas located on a common substrate, where each well area is defined by at least three bank structures that form the side walls of the well area. Within each well area, there are at least two electrode segments where the electrode segments are separated laterally by at least one insulating bank where the insulating bank(s) are thicker than the electrode segments. There is at least one charge transporting layer completely filling the well area in direct contact and overlying both the electrode segments and the insulating bank(s). The well areas are filled using solution methods such as inkjet. Such devices have improved uniformity across the active areas.

Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side and an active area on the second side of the die. The semiconductor packages may also include two or more bumps coupled to two or more die pads on a second side of the die. The semiconductor packages may include an optically transmissive lid coupled to the semiconductor die through an adhesive, two or more bumps, and a first redistribution layer (RDL). The semiconductor package may include a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die. The second RDL may extend to the first side of the semiconductor die. The first RDL may extend to an edge of the semiconductor die.

Abstract: A method for manufacturing a plurality of surface mounted optoelectronic devices and a surface mounted optoelectronic device are disclosed. In an embodiment, a surface mounted optoelectronic device includes a transparent base body having a mounting rear side, a radiation exit side opposite the mounting rear side, and mounting side surfaces which are each disposed transversely to the radiation exit side, a semiconductor layer sequence disposed laterally to at least one mounting side surface and a terminal contact extending from the at least one mounting side surface to the mounting rear side, wherein the semiconductor layer sequence includes an active region configured to emit radiation so that the radiation decouples from the surface mounted optoelectronic device via the radiation exit side of the base body.

Abstract: The present disclosure provides methods for forming a channel structure in a film stack for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and a channel structure formed in the film stack, wherein the channel structure is filled with a channel layer and a protective blocking layer, wherein the channel layer has a gradient dopant concentration along a vertical stacking of the film stack.

Abstract: A display device includes a substrate, a first data line, a scan line, a first sub-pixel, a passivation layer, and a common electrode. The first sub-pixel includes a first main-driving element, a first sub-driving element, a first capacitor electrode, and a first pixel electrode. The first main-driving element includes a first main-gate, a first main-channel layer, a first main-source, and a first main-drain. The first sub-driving element includes a first sub-gate, a first sub-channel layer, a first sub-source, and a first sub-drain. The first capacitor electrode is electrically connected with the first main-drain and the first sub-source. The first pixel electrode is electrically connected with the first sub-drain. The common electrode and the first capacitor electrode have a first main capacitor therebetween. The common electrode and the first pixel electrode have a first sub capacitor therebetween.

Abstract: A display substrate and a manufacturing method thereof, and a display panel are disclosed. The display substrate includes a base substrate and a pixel driving circuit on the base substrate; and the pixel driving circuit includes a driving transistor and a gate leading line, the driving transistor includes a gate electrode, the gate leading line is electrically connected to the gate electrode, and the gate leading line is between the gate electrode and the base substrate.

Abstract: The present disclosure provides a flexible display device and a manufacturing method thereof. The flexible display device includes a base substrate; a pixel defining layer disposed on the base substrate defining a plurality of light emitting regions; and a first electrode layer disposed on a side of the pixel defining layer away from the base substrate and in light-emitting regions. A thin film encapsulation layer covers the first electrode layer and has protrusions protruding toward the pixel defining layer at a plurality of positions.

Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.

Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.

Abstract: A display panel includes: a first substrate including an opening area, a display area, and a non-display area; a plurality of display elements arranged in the display area; a second substrate facing the first substrate with the plurality of display elements therebetween; a sealing member arranged between the first substrate and the second substrate; a first conductive line between the opening area and the display area, the first conductive line being located in the non-display area; a second conductive line located in the non-display area; and at least one insulating layer arranged between the first conductive line and the second conductive line.

Abstract: A display panel includes: a substrate including an opening area, a display area surrounding the opening area, and an intermediate area between the opening area and the display area; a plurality of display elements in the display area and electrically connected to a thin film transistor; a plurality of wirings arranged along an edge of the opening area in the intermediate area; and at least one metal pattern spaced apart from the plurality of wirings in the intermediate area, the at least one metal pattern surrounding the opening area and having a ring shape opened at one side.

Abstract: A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Abstract: A display device that includes a substrate having a display area configured for displaying an image and a peripheral area positioned outside of the display area. A first thin film transistor is disposed on the display area. A display element is electrically connected to the first thin film transistor. The display element includes a pixel electrode, an intermediate layer, and an opposite electrode. An embedded driving circuit portion is disposed on the peripheral area. The embedded driving circuit portion includes a second thin film transistor. A common voltage supply line is disposed on the peripheral area. The common voltage supply line is positioned closer to the display area than the embedded driving circuit portion. The common voltage supply line is electrically connected to the opposite electrode.