Abstract: An organic photoelectric conversion element, an imaging device, and an optical sensor, which can detect a plurality of wavelength regions by a single element structure, are provided. The photoelectric conversion element is formed by providing an organic photoelectric conversion portion including two or more types of organic semiconductor materials having different spectral sensitivities between the first and the second electrodes. Wavelength sensitivity characteristics of the photoelectric conversion element change according to a voltage (bias voltage) applied between the first and the second electrodes. The photoelectric conversion element is mounted in the imaging device and the optical sensor.

Abstract: An embodiment of a method of manufacturing a semiconductor device includes providing a semiconductor material that comprises SiC and forming an electrically conductive contact layer on the semiconductor material. A non-ohmic contact is formed between the semiconductor material and the electrically conductive contact layer. The electrically conductive contact layer comprises a metal nitride with a nitrogen content between 10 to 50 atomic %. Additional embodiments of manufacturing a semiconductor device are described.

Abstract: Disclosed is an organic electroluminescent display panel, a method for manufacturing the same and a display apparatus. The organic electroluminescent display panel comprises a plurality of luminescent units, wherein light-isolating members are disposed between the plurality of luminescent units for isolating light emitted from the respective luminescent units. Therefore, the organic electroluminescent display panel, the method for manufacturing the same and the display apparatus according to the present invention can prevent mutual interference between the light from the respective luminescent units of the organic electroluminescent display panel.

Abstract: A semiconductor substrate (1) includes a region (AR3) between a region (AR1) and a region (AR2), a control gate electrode (CG) is formed on an upper surface (TS1) of the region (AR1), and a memory gate electrode (MG) is formed on an upper surface (TS2) of the region (AR2). The upper surface (TS2) is lower than the upper surface (TS1), and the region (AR3) has a connection surface (TS3) connecting the upper surface (TS1) and the upper surface (TS2). An end (EP1) of the connection surface (TS3) which is on the upper surface (TS2) side is arranged closer to the memory gate electrode (MG) than an end (EP2) of the connection surface (TS3) which is on the upper surface (TS1) side, and is arranged lower than the end (EP2).

Abstract: A display device includes a substrate including a display area to display an image and a non-display area provided on at least one side of the display area, a plurality of pixels disposed on the substrate and provided in an area corresponding to the display area, a first insulating layer having an opening in a first area of the non-display area, a second insulating layer provided in the first area, first lines provided on the substrate and connected to the plurality of pixels, and second lines provided on the first and second insulating layers, and connected to the first lines. An area in which the first lines overlap with the second lines is spaced apart from an edge of the second insulating layer when viewed in a plan view.

Abstract: A display module is provided including a pixel region having a plurality of pixels and a black matrix arranged outside the pixel region. Each of the pixels is separated from adjacent pixels by a first interval, a left distance from the left edge to a first one of the plurality of pixels plus a right distance from a second one of the plurality of pixels to the right edge is a first distance, and a bottom distance from the bottom edge to a third one of the plurality of pixels plus a top distance from a fourth one of the plurality of pixels to the top edge is the first distance.

Abstract: A thin film transistor array substrate and an organic light emitting diode (OLED) display device including the same are disclosed in which a color layer is disposed on a first substrate corresponding to a white sub-pixel and a non color filter area is included in a second substrate corresponding to the white sub-pixel, and thus, it is possible to lower an amount of reflectance of external light, increase a luminance efficiency, and reduce a power consumption of the OLED display device.

Abstract: The present disclosure provides a top-emitting white organic light emitting diode (OLED) device, a method for manufacturing the same and a display apparatus. The OLED device includes a plurality of pixel units on a substrate, wherein each pixel unit includes a first electrode layer, an organic layer and a second electrode layer arranged subsequently on the substrate from bottom up, and the organic layer in each pixel unit includes a gradually-varied cavity length, and the gradually-varied cavity length corresponds to a range from a wavelength of red light to a wavelength of blue light.

Abstract: Converter output terminals of a converter are located adjacent to each other on a first side and an external terminal for external connection of a composite module is located adjacent to the converter output terminal. AC input terminals of the converter are located on a second side. Each of the distances between the converter output terminals and between the converter output terminal and the external terminal is set to a first formation pitch. Each of the distances between the AC input terminals is set to a second formation pitch. The first formation pitch is set to be equal to the second formation pitch.

Abstract: A thin-film device includes a resin film which includes a first surface and a second surface facing the first surface, a first inorganic layer on the first surface, a thin-film element on the first inorganic layer, and a second inorganic layer on the second surface, wherein a film density of the second inorganic layer is greater than a film density of the first inorganic layer.

Abstract: An ink for forming a functional layer includes a first component that contains at least one kind of aromatic solvent of which a boiling point is higher than or equal to 250° C. and lower than or equal to 350° C., a second component that contains at least one kind of aliphatic solvent of which a boiling point is higher than or equal to 200° C., and a third component for forming a positive hole injection layer, in which a solubility of the third component in the first component is higher than the solubility of the third component in the second component, a mixing ratio of the second component is 30 vol %, the boiling point of the first component is higher than the boiling point of the second component, and a difference between the boiling points thereof is higher than or equal to 30° C.

Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.

Abstract: An EL light-emitting element in which a lower electrode layer, an EL layer, and an upper electrode layer are stacked is formed on a substrate, and a wiring is formed on a counter substrate. Further, the substrate and the counter substrate are bonded so that the wiring is in physical contact with the upper electrode layer of the EL element. Accordingly, the wiring can serve as an auxiliary wiring for increasing conductivity of the upper electrode layer. With such an auxiliary wiring, a potential drop due to the resistance of the upper electrode layer can be suppressed even in the light-emitting device whose light-emitting portion is large.

Abstract: A display device includes a substrate having an edge portion, a display region located on the substrate and separated from the edge portion, a drive circuit region between the display region and the edge portion, a terminal region on the edge portion; and wirings in the display region, the drive circuit region, and an area between the drive circuit region and the terminal region, wherein at least one wiring of the wirings include a first conductive layer, a second conductive layer overlapping the first conductive layer in a plan view and separated from the first conductive layer, a first connection portion where the first conductive layer and the second conductive layer are electrically connected, a second connection portion where the first conductive layer and the second conductive layer are electrically connected, and the first connection portion is separated from the second connection portion.

Abstract: Disclosed is an organic light emitting display device that may include an anode electrode and an eave structure under a bank layer and spaced apart from each other, a cathode electrode on the bank layer, and an auxiliary electrode under the eave structure and electrically connected with the cathode electrode, wherein the cathode electrode extends to a contact space under the eave structure, and the extending cathode electrode is connected with the auxiliary electrode in the contact space.

Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.

Abstract: A method of fabricating advanced multi-threshold field effect transistors using a replacement metal gate process. A first method includes thinning layers composed of multilayer film stacks and incorporating a portion of the remaining thinned film in some transistors. A second method includes patterning dopant materials for a high-k dielectric by using thinning layers composed of multilayer thin film stacks, or in other embodiments, by a single thinning layer.

Abstract: A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.

Abstract: A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.

Abstract: A method for manufacturing a surface-mount type package whose face parallel with the semiconductor chip surface has a circular cross-section, is characterized by including at least the following steps in this order: a first step in which a semiconductor chip is bonded onto a circular support substrate; a second step in which the semiconductor chip is sealed with resin; a third step in which the resin covering the pads of the semiconductor chip is removed; a fourth step in which a rewiring layer is formed; and a fifth step in which bumps are formed. The method can provide a surface-mount type package for semiconductor chips which is resistant to failures caused by thermal stress.