Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices.

Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.

Abstract: The present invention discloses an OLED array substrate and a manufacturing method thereof, a display apparatus. The OLED array substrate includes a TFT and an OLED. The method includes: forming an oxide semiconductor layer by a film forming process, and performing one patterning process on the oxide semiconductor layer to form an active layer of the TFT and a first electrode of the OLED; sequentially forming a first insulating layer and a second insulating layer on the active layer and the first electrode of the OLED, the first insulating layer being a lyophilic layer, and the second insulating layer being a lyophobic layer; forming an accommodation cavity exposing the first electrode by performing a patterning process on the first and second insulating layers; and injecting, into the accommodation cavity, and drying a solution containing an organic light emitting material to form an organic light emitting material layer.

Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins.

Abstract: An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon via. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon via. The isolation film is thinned to re-expose the through-silicon via, and conductive elements are formed on the through-silicon via. The conductive element may be, for example, a solder ball or a conductive pad. The conductive pad may be formed by depositing a seed layer and an overlying mask layer. The conductive pad is formed on the exposed seed layer. Thereafter, the mask layer and the unused seed layer may be removed.

Abstract: Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. The at least one diode may be formed from a single crystalline silicon material. Methods of forming such semiconductor devices are also disclosed.

Abstract: A method of fabricating a semiconductor structure. The method includes forming a dummy structure over a semiconductor body. The method further includes depositing an inter-layer dielectric (ILD) over the semiconductor body. The method further includes removing a dummy material of the dummy structure to form an opening in the ILD. The method further includes filling the opening with a dielectric material to form a dielectric structure. The method further includes stacking a plurality of interconnect elements over the dielectric structure.

Abstract: This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to each other, a touch plate having a second top surface and a second bottom surface opposite to each other, formed above the sensing chip, and a color layer, sandwiched between the sensing chip and the touch plate, wherein the sensing chip comprises a sensing device formed nearby the first top surface and a plurality of conductive pads formed nearby the first top surface and adjacent to the sensing device, a plurality of through silicon vias exposing their corresponding conductive pads formed on the first bottom surface, a plurality of conductive structures formed on the first bottom surface, and a re-distribution layer overlaying the first bottom surface and each through silicon via to electrically connect each conductive pad and each conductive structure.

Abstract: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.

Abstract: A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.

Abstract: A high efficacy multi-layer seal structure formed on an organic light emitting diode device and the process for depositing the same. A thin film seal is formed over the substrate having OLED layers, and includes a first metallic layer formed over the substrate, an inorganic layer formed over the first metallic layer, and a second metallic layer formed of the inorganic layer. The metallic layers comprise one or more oxide or nitride layers, each oxide or nitride comprising a metal. The inorganic layer comprises a metal oxide, a metal nitride or a metal oxynitride. The process for forming the multi-layer seal structure includes depositing the first metallic layer over the substrate using atomic layer deposition, depositing the inorganic layer over the first metallic layer using sputtering, and then depositing the second metallic layer over the inorganic layer using atomic layer deposition.

Abstract: A semiconductor substrate processing apparatus includes a vacuum chamber having a processing zone in which a semiconductor substrate may be processed, a process gas source in fluid communication with the vacuum chamber for supplying a process gas into the vacuum chamber, a showerhead module through which process gas from the process gas source is supplied to the processing zone of the vacuum chamber, and a substrate pedestal module. The substrate pedestal module includes a pedestal made of ceramic material having an upper surface configured to support a semiconductor substrate thereon during processing, a stem made of ceramic material, and a backside gas tube made of metallized ceramic material that is located in an interior of the stem. The metallized ceramic tube can be used to deliver backside gas to the substrate and supply RF power to an embedded electrode in the pedestal.

Abstract: A package frame includes a plurality of unit regions disposed on one surface of the package frame, a peripheral region surrounding the unit regions on the one surface, and a wrinkled structure disposed on the one surface in the peripheral region. A first surface of the wrinkled structure extends from the one surface and is disposed at a different level than the one surface. Each of the unit regions includes a plurality of conductive pads.

Abstract: An organic light emitting diode display device can include a display panel including a plurality of pixels, at least one pixel among the plurality of pixels including first to fourth sub-pixels defined at intersection regions between gate lines and data lines; and first to third color filter layers corresponding to the first sub-pixel, the third sub-pixel and the fourth sub-pixel, respectively; the second sub-pixel includes: an emission area, and first and second color filter patterns disposed in the second sub-pixel configured to absorb light incident from an outside of the organic light emitting diode display device, the first color filter pattern and a second color filter pattern are different colors; and the first color filter pattern or the second color filter pattern has a first gap between an edge of the first or second color filter pattern and an edge of the emission area.

Abstract: A semiconductor device includes a gate trench in a semiconductor substrate, a source trench in the semiconductor substrate, the source trench having a first portion and a second portion under the first portion, where the first portion of the source trench is wider than the gate trench, and extends to a depth of the gate trench. The semiconductor device also includes a gate electrode and a gate trench dielectric liner in the gate trench, and a conductive filler and a source trench dielectric liner in the source trench. The semiconductor device further includes a source region between the gate trench and the source trench, a base region between the gate trench and the source trench, and a source contact coupled to the source region and the base region.

Abstract: This invention provides a thin film transistor and a manufacturing method thereof, an array substrate, and a display apparatus. This thin film transistor comprises an organic semiconductor layer and a source drain electrode layer, and further comprises a metal oxide insulating layer, wherein the metal oxide insulating layer is provided between the organic semiconductor layer and the source drain electrode layer and has a work function higher than that of the source drain electrode layer. In the thin film transistor provided by this invention, the metal oxide insulating layer having a higher work function can generate an interface dipole barrier so as to reduce the difficulty for the carriers in the source drain electrode to enter the organic semiconductor layer and thereby it is possible to decrease the contact resistance between the source drain electrode layer and the semiconductor layer and improve electrical properties of the thin film transistor.

Abstract: Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively.

Abstract: A display apparatus includes a substrate including at least one hole disposed in a hole area of the substrate, a thin film transistor disposed on the substrate, a light-emitting component disposed on the substrate and electrically connected to the thin film transistor, an insulating layer disposed on the substrate, a thin film encapsulation layer disposed on the substrate, and a laser blocking layer. The substrate includes a display area and a non-display area that is disposed between the display area and the hole area. The laser blocking layer is disposed on the insulating layer in the non-display area.

Abstract: Disclosed are a TFT array substrate, a method for fabricating the same and a display device. The TFT array substrate includes a plurality of pixel units, each of the plurality of pixel units includes a common electrode (9). The common electrode (9), is comb-shaped, and includes a plurality of strip electrodes and a plurality of slits. Each of the strip electrodes is configured for reflecting light incident on the strip electrode, and each of the slits is configured for transmitting light incident on the slit. As the comb-shaped common electrode with both a reflective region and a transmissive region is formed through a single patterning process, the fabrication process is simplified and the fabrication cost and difficulty are reduced.