Abstract: An organic light emitting diode display includes a substrate and a first red organic light emitting element disposed on the substrate. The first red organic light emitting element may include a first light emission region and a second light emission region, wherein the first light emission region emits a first red light having a first peak wavelength, and the second light emission region emits a second red light having a second peak wavelength different from the first peak wavelength.

Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

Abstract: A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.

Abstract: A light-emitting element having high emission efficiency which includes a fluorescent material as a light-emitting substance is provided. A light-emitting element includes a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a light-emitting layer. The light-emitting layer includes a host material and a guest material. The host material has a difference of more than 0 eV and less than or equal to 0.2 eV between a singlet excitation energy level and a triplet excitation energy level. The guest material is capable of emitting fluorescence. The triplet excitation energy level of the host material is higher than a triplet excitation energy level of the guest material.

Abstract: An organic layer depositing apparatus includes a deposition unit which includes one or more deposition assemblies spaced a predetermined distance apart from a substrate to deposit a deposition material on the substrate, wherein the one or more deposition assemblies include: a deposition source; a deposition source nozzle unit; a first pattern sheet which includes a first patterning unit and a first overlap unit; and a second pattern sheet which includes a second patterning unit and a second overlap unit, wherein the first and second pattern sheets are arranged such that the first and second overlap units overlap each other.

Abstract: Methods of forming silicon germanium tin (SixGe1-xSny) films are disclosed. Exemplary methods include growing films including silicon, germanium and tin in an epitaxial chemical vapor deposition reactor. Exemplary methods are suitable for high volume manufacturing. Also disclosed are structures and devices including silicon germanium tin films.

Abstract: An organic light-emitting display apparatus includes an organic light-emitting device including a first electrode, an intermediate layer including a light-emitting layer, and a second electrode; an organic barrier layer on the second electrode of the organic light-emitting device and having a first side facing the organic light-emitting device and a second side facing in an opposite direction from the first side; a buffer layer contacting the second side of the organic barrier layer; and a first inorganic barrier layer on the second side of the organic barrier layer with the buffer layer therebetween, wherein a water vapor transmission rate of the buffer layer is greater than 10?2 g/(cm2·day).

Abstract: A semiconductor module includes upper arms and lower arms for three phases, heat sinks, a main circuit side bus bar, an output terminal side bus bar, a control terminal, and a resin mold portion. The output terminal side bus bar includes U-phase to W-phase wiring layers disposed opposite to each other via an insulating layer and U to W terminals electrically connecting each of the U-phase to W-phase wiring layer and a load. A stacked layer number of the U-phase to W-phase wiring layer is set to be an even number.

Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

Abstract: An organic light emitting diode includes: a first electrode; a hole transport region disposed on the first electrode; an emitting layer disposed on the hole transport region, the emitting layer configured to emit light; an electron transport region disposed on the emitting layer; a second electrode disposed on the electron transport region; a capping layer disposed on the second electrode; and a compensation layer disposed on the capping layer, the compensation layer including a compensation pattern, wherein the compensation pattern is configured to compensate a phase of an inclined light, and wherein the inclined light is a light emitted from the emitting layer.

Abstract: A display apparatus includes a first substrate; a display device including a display portion and located on the first substrate; a second substrate located above the display device; a sealing portion between the first substrate and the second substrate, and surrounding the display portion, the sealing portion bonding the first substrate and the second substrate; a circuit portion located between the sealing portion and the display portion; and one or more supplement members located between the circuit portion and the sealing portion so as to absorb an external shock delivered to the sealing portion.

Abstract: The disclosure relates to organic field effect transistors, and methods for producing organic field effect transistors. The organic field effect transistors may include a first electrode, and a second electrode, the electrodes providing a source electrode and a drain electrode, an intrinsic organic semiconducting layer in electrical contact with the first and second electrode, a gate electrode, a gate insulator provided between the gate electrode and the intrinsic organic semiconducting layer, and a doped organic semiconducting layer including an organic matrix material and an organic dopant.

Abstract: A bank partitions a plurality of pixels and has an opening in each of the plurality of pixels. An organic layer includes a light emitting layer, and covers the bank opening. A first inorganic barrier layer is formed of an inorganic material, and covers the bank and the organic layer. A plurality of organic barrier portions are formed of organic materials, and are disposed on the first inorganic barrier layer. A second inorganic barrier layer is formed of the inorganic material, and covers the first inorganic barrier layer and the plurality of organic barrier portions. A recessed portion is formed on the bank and the first inorganic barrier layer (for example, the recessed portion is formed in an area which covers a contact hole), and a portion of the organic barrier portion is formed in the recessed portion.

Abstract: Embodiments of the present disclosure provide an apparatus comprising an integrated circuit with a chip-on-chip and chip-on-substrate configuration. In one instance, the apparatus may include an optical transceiver with an opto-electronic component disposed in a first portion of a die, and a trace coupled with the opto-electronic component and disposed to extend to a surface in a second portion of the die adjacent to the first portion, to provide electrical connection for the integrated circuit and another integrated circuit to be coupled with the second portion of the die in a chip-on-chip configuration. The apparatus may include a second trace disposed in the second portion of the die to extend to the surface in the second portion, to provide electrical connection for the other integrated circuit and a substrate to be coupled with the second portion of the die in a chip-on-substrate configuration. Other embodiments may be described and/or claimed.

Abstract: A display panel includes a substrate, light emitting structures disposed on an upper surface of the substrate in pixel regions, an encapsulation substrate disposed over the light emitting structures, and a light blocking member disposed on a lower surface of the substrate. The light blocking member has blocking portions corresponding to the pixel regions and openings corresponding to transparent regions.

Abstract: An organic light emitting diode display includes a substrate, a scan line on the substrate for transferring a scan signal, a data line crossing the scan line and for transferring a data signal, a driving voltage line crossing the scan line and for transferring a driving voltage, a switching thin film transistor coupled to the scan line and the data line, a driving thin film transistor coupled to a switching drain electrode of the switching thin film transistor, and an organic light emitting diode (OLED) coupled to a driving drain electrode of the driving thin film transistor, wherein a driving semiconductor layer of the driving thin film transistor is bent and in a plane substantially parallel to the substrate.

Abstract: A display device includes a display panel, and a protection film on the display panel and including a base film, and a plurality of protrusions on the base film.

Abstract: An organic light emitting diode (OLED) display includes a substrate including a penetrated portion positioned in a display area for displaying an image and a light emission region neighboring the penetrated portion. The OLED display also includes an OLED positioned on the light emission region of the substrate.

Abstract: A silicon-on-sapphire chip with minimal thermal strain preload is provided. The chip includes a sapphire substrate having a first-sapphire surface and an opposing second-sapphire surface; and a silicon layer overlaying the first-sapphire surface. The silicon layer is formed by: creating a plurality of buried cavities in a plane within tens of microns from a first-silicon surface of a silicon wafer; laser fusing the first-silicon surface to the first-sapphire surface at room temperature to attach the silicon wafer to a sapphire wafer; and cleaving the silicon wafer along the plane including the plurality of buried cavities. A silicon-wafer layer is formed from the silicon material between the first-silicon surface and the plane of the plurality of buried cavities. The silicon-wafer layer and the sapphire wafer form a silicon-on-sapphire wafer. The silicon-on-sapphire chip is formed by dicing the silicon-on-sapphire wafer.