Abstract: Disclosed is a light emitting diode using light of a short wavelength band. The light emitting diode includes a first conductivity type semiconductor layer having a front side and a back side, a second conductivity type semiconductor layer having a front side and a back side, an active layer formed between the back side of the first conductivity type semiconductor layer and the front side of the second conductivity type semiconductor layer, a first electrode electrically connected to the first conductivity type semiconductor layer, a second conductivity type reflective layer formed on the back side of the second conductivity type semiconductor layer, and a reflective part formed on the second conductivity type reflective layer to reflect light of a short wavelength band and light of a blue wavelength band and electrically connected to the second conductivity type semiconductor layer. The second conductivity type reflective layer includes DBR unit layers.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

Abstract: A method for manufacturing a semiconductor device in accordance with various embodiments may include: forming an opening in a first region of a semiconductor substrate, the opening having at least one sidewall and a bottom; implanting dopant atoms into the at least one sidewall and the bottom of the opening; configuring at least a portion of a second region of the semiconductor substrate laterally adjacent to the first region as at least one of an amorphous or polycrystalline region; and forming an interconnect over at least one of the first and second regions of the semiconductor substrate.

Abstract: A method for manufacturing a display device, includes preparing a display panel including a base substrate, an encapsulation layer facing the base substrate, and an organic light emitting device formed between one surface of the base substrate and the encapsulation layer, attaching a support layer to the other surface of the base substrate through an adhesive layer, curing the adhesive layer through irradiation of UV light, and mounting a driving chip on one surface of the display panel. The adhesive layer includes an acryl-based compound, a UV curable compound, and a photoinitiator.

Abstract: A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder bumps comprises eutectic Sn—Bi compound, and the eutectic Sn—Bi compound is free of Ag. The method further includes stretching the solder bump to increase a height of the solder bump, wherein stretching the solder bump forms lamellar structures having a contact angle of less than 90°. The method further includes cooling down the solder bump.

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

Abstract: An organic light-emitting diode display includes an organic light-emitting display device including a first electrode, an intermediate layer including an organic emission layer, and a second electrode; a first inorganic encapsulation layer on the second electrode; a second inorganic encapsulation layer on the first inorganic encapsulation layer; and an organic encapsulation layer on the second inorganic encapsulation layer. A refractive index of the first inorganic encapsulation layer is higher than a refractive index of the second inorganic encapsulation layer. The first inorganic encapsulation layer has an extinction coefficient of 0.02 to 0.07 and a refractive index of 2.1 to 2.3 at a blue wavelength.

Abstract: Provided is an organic EL display device (electroluminescence device) including a TFT substrate (substrate) and an organic EL element (electroluminescence device) provided on the TFT substrate, wherein the organic EL display device includes a sealing layer that seals the organic EL element. The sealing layer is provided with a first, a second, and a third sealing film that are sequentially stacked from the organic EL element side, the first and third sealing films are each formed of an inorganic film, and the second sealing film is formed of an octamethylcyclotetrasiloxane film.

Abstract: An organic light-emitting display apparatus, including a lower substrate having a peripheral area, which includes a first peripheral part and a second peripheral part, and a display area between the first peripheral part and the second peripheral part; an upper substrate on the lower substrate; a sealing member between the lower substrate and the upper substrate and on the lower substrate in the peripheral area; and a first material layer between the sealing member and the lower substrate and including a first opening pattern at the first peripheral part and a second opening pattern at the second peripheral part, the second opening pattern having a smaller size than the first opening pattern.

Abstract: A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.

Abstract: An organic light emitting diode display device includes a first driving voltage line including a first portion extending in a first direction and a second portion having a larger width than the first portion in a second direction perpendicular to the first direction. The second portion overlaps a gate electrode of a driving thin film transistor, an interlayer insulating layer is between the second portion and the gate electrode of the driving thin film transistor.

Abstract: A method of forming a FinFET is provided. A gate oxide layer and a dummy poly layer are substantially simultaneously etched using an etchant having a higher selectivity on the gate oxide layer than on the dummy poly layer. The gate oxide layer and the dummy poly layer are intersected with the gate oxide layer over a fin layer of the FinFET.

Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

Abstract: A display apparatus including a display panel, a buffer, and a curved buffer. The display panel includes a curved portion connected to a flat portion. The buffer overlaps the flat portion and having a first thickness. The curved buffer is on a same layer as the buffer and overlaps the curved portion, the curved buffer having a second thickness greater than the first thickness.

Abstract: Embodiments of a microelectronic packaged device and methods of making are provided, where the microelectronic packaged device includes a system package comprising a first die and a second die, wherein the first die and the second die are laterally positioned to one another, and the first die and the second die are laterally separated from one another by mold compound; and a conductive trace formed between a first conductive surface on an exposed surface of the first die and a second conductive surface on an exposed surface of the second die, wherein the conductive trace is laser sintered directly on the first conductive surface, on a portion of the exposed surface of the first die, on a portion of a top surface of the mold compound, on a portion of the exposed surface of the second die, and on the second conductive surface.

Abstract: A MEMS device and methods of forming are provided. A dielectric layer of a first substrate is patterned to expose conductive features and a bottom layer through the dielectric layer. A first surface of a second substrate is bonded to the dielectric layer and the second substrate is patterned to form a membrane and a movable element. A cap wafer is bonded to the second substrate, where bonding the cap wafer to the second substrate forms a first sealed cavity comprising the movable element and a second sealed cavity that is partially bounded by the membrane. Portions of the cap wafer are removed to expose the second sealed cavity to ambient pressure.

Abstract: A wavelength conversion film is provided and may include a first layer including a wavelength conversion material and an encapsulant encapsulating the wavelength conversion material, and a second layer attached to the first layer and having a refractive index less than a refractive index of the encapsulant and greater than a refractive index of air.

Abstract: Provided is a technique of forming a film containing a first element and a second element on a substrate by performing a cycle a predetermined number of times. The cycle includes: (a) supplying a hydro-based precursor containing the first element and a halogen-based precursor containing the second element into a process chamber accommodating a substrate to confine the hydro-based precursor and the halogen-based precursor in the process chamber; (b) maintaining a state where the hydro-based precursor and the halogen-based precursor are confined in the process chamber; and (c) exhausting the process chamber.

Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer.