Patents Examined by Lisa Kilday
  • Patent number: 7038328
    Abstract: The present invention relates to an anti-reflective coating composition characterized by comprising a resin made from triazine compounds having at least two nitrogen atoms substituted a hydroxymethyl group and/or an alkoxymethyl group, and a light absorbing compound and/or a light absorbing resin. The present invention offers an anti-reflective coating composition for the anti-reflective coating having high light absorption property of the light used for the lithography process in the preparation of semiconductor device, showing high reflective light preventing effect, being used at thinner film thickness more than before, and having greater dry etching rate in comparison to photoresist layer.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: May 2, 2006
    Assignee: Brewer Science Inc.
    Inventors: Tomoyuki Enomoto, Keisuke Nakayama, Rama Puligadda
  • Patent number: 6979580
    Abstract: A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device can be fabricated using silicon based substrates and along with other types of devices.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: December 27, 2005
    Assignee: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • Patent number: 6962882
    Abstract: While a crucible containing an Si material and a substrate to be processed are set in a chamber, Ar gas is supplied into the chamber and the Si material is evaporated by heating, thereby forming a nanoparticle thin film of Si on the substrate. This substrate is then annealed in an oxygen atmosphere to oxidize Si, forming a nanoparticle oxide thin film consisting of SiO2.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: November 8, 2005
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
  • Patent number: 6943127
    Abstract: A low dielectric constant film having silicon-carbon bonds and dielectric constant of about 3.0 or less, preferably about 2.5 or less, is provided. The low dielectric constant film is deposited by reacting a cyclic organosilicon compound and an aliphatic organosilicon compound with an oxidizing gas while applying RF power. The carbon content of the deposited film is between about 10 and about 30 atomic percent excluding hydrogen atoms, and is preferably between about 10 and about 20 atomic percent excluding hydrogen atoms.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: September 13, 2005
    Assignee: Applied Materials Inc.
    Inventors: Seon-Mee Cho, Peter Wai-Man Lee, Chi-I Lang, Dian Sugiarto, Chen-An Chen, Li-Qun Xia, Shankar Venkataraman, Ellie Yieh
  • Patent number: 6900144
    Abstract: A film-forming surface reforming method includes the steps of bringing a gas or an aqueous solution containing ammonia, hydrazine, an amine, an amino compound or a derivative thereof into contact with the film-forming surface before an insulating film is formed on the film-forming surface, and bringing a gas or an aqueous solution containing Hydrogen peroxide, ozone, Oxygen, nitric acid, sulfuric acid or a derivative thereof into contact with the film-forming surface.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: May 31, 2005
    Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.
    Inventors: Kazuo Maeda, Setsu Suzuki, Takayoshi Azumi, Kiyotaka Sasaki
  • Patent number: 6887724
    Abstract: To provide a TEG capable of early stage feedback of testing contents and a method of testing using the TEG. TFTs for TEG are manufactured on a different substrate than actual panel TFTs by using from among processes for manufacturing actual panel TFTs, processes that may easily lead to dispersion in the TFT characteristics, and the minimum number of processing steps necessary for TFT manufacture. The number of processing steps is fewer than the number for the actual panel, and therefore it is possible to complete the TFTs for TEG quicker than those of the actual panel, and it becomes possible to feed back an evaluation of the TEG TFT characteristics to the actual panel manufacturing process at an early stage. Time and costs associated with manufacture of the actual panel can therefore be suppressed.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: May 3, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Nakamura, Mai Akiba
  • Patent number: 6887749
    Abstract: Methods are provided for fabricating multiple oxide thicknesses on a single silicon wafer. Methods are provided to form multiple gate oxide thicknesses on a single chip wherein the chip can include circuitry encompassing a range of technologies including but not limited to the memory and logic technologies. These methods can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Methods for forming a semiconductor device include forming a top layer of SiO2 on a top surface of a silicon wafer. A trench layer of SiO2 is also formed on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. Additionally, the formation of the top and trench layers of SiO2 are such that a thickness of the top layer is different from a thickness of the trench layer.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: May 3, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Wendell P. Noble, Leonard Forbes
  • Patent number: 6884740
    Abstract: Photoelectrochemical (PEC) etching is restricted to a group III nitride semiconductor-barrier interface to laterally etch or undercut the target group III nitride. The barrier interface is provided by the transparent sapphire substrate on which the target group III nitride is epitaxially grown or by a layer of material in intimate contact with the target group III nitride material and having a bandgap sufficiently high to make it resistant to PEC etching. Due to the first orientation in which this effect was first observed, it has been named backside-Illuminated photoelectrochemical (BIPEC) etching. It refers to a preferential etching at the semiconductor-barrier layer interface. The assembly can be exposed to light from any direction to effectuate bandgap-selective PEC etching. An opaque mask can be applied to limit the lateral extent of the photoelectrochemical etching.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: April 26, 2005
    Assignee: The Regents of the University of California
    Inventors: Evelyn L. Hu, Andreas R. Stonas
  • Patent number: 6875692
    Abstract: A method of forming a copper structure, comprising the following steps. A substrate is provided. A patterned dielectric layer is formed over the substrate with the patterned dielectric layer having an opening exposing a portion of the substrate. The opening having exposed sidewalls. A Sn layer is formed directly upon the exposed sidewalls of the opening. A copper seed layer is formed upon the Sn layer within the opening. A bulk copper layer is formed over the copper seed layer, filling the opening. The structure is thermally annealed whereby Sn diffuses from the Sn layer into the copper seed layer and the bulk copper layer forming CuSn alloy within the copper seed layer and the bulk copper layer.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: April 5, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Liang Chang, Shaulin Shue
  • Patent number: 6855642
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: February 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Patent number: 6855581
    Abstract: The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: February 15, 2005
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Tae Moon Roh, Dae Woo Lee, Yil Suk Yang, Il Yong Park, Sang Gi Kim, Jin Gun Koo, Jong Dae Kim
  • Patent number: 6852650
    Abstract: An insulation film is formed on a semiconductor substrate by vaporizing a silicon-containing hydrocarbon compound to provide a source gas, introducing a reaction gas composed of the source gas and an additive gas such as an inert gas and oxidizing gas to a reaction space of a plasma CVD apparatus. The residence time of the reaction gas in the reaction space is lengthened by reducing the total flow of the reaction gas in such a way as to form a siloxan polymer film with a low dielectric constant.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: February 8, 2005
    Assignee: ASM Japan K.K.
    Inventors: Nobuo Matsuki, Yasuyoshi Hyodo, Masashi Yamaguchi, Yoshinori Morisada, Atsuki Fukazawa, Manabu Kato
  • Patent number: 6849518
    Abstract: A method and apparatus for forming shallow and deep isolation trenches in a substrate so that the shallow and deep isolation trenches are aligned without mis-registration. The method includes forming a plurality of shallow trenches, covering a portion of the plurality of shallow trenches, then etching the uncovered shallow trenches to create deeper trenches.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: February 1, 2005
    Assignee: Intel Corporation
    Inventors: Krishna Parat, Kiran Pangal, Allen Lu
  • Patent number: 6849483
    Abstract: A charge trapping device, and a method of forming the same is disclosed. Charge traps are optimally distributed through a trapping region based on controlling various conventional processing operations, such as an implant, an anneal, an insulator film deposition, and the like. In some embodiments, FETs can be configured to include a negative differential resistance (NDR) characteristic when they utilize a particular charge trap energy and distribution.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: February 1, 2005
    Assignee: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • Patent number: 6846730
    Abstract: A method of etching nitride over oxide is provided for the formation of vertical profile nitride spacers with high uniformity while maintaining the integrity of underlying thin oxide layers. The method includes providing a first gas flow including a first fluorocarbon and a second fluorocarbon at a first ratio, applying a first quantity of power to the first gas flow to create a first plasma, etching a first portion of a silicon nitride layer with the first plasma, providing a second gas flow including the first fluorocarbon and the second fluorocarbon at a second ratio greater than the first ratio, applying a second quantity of power to the second gas flow to create a second plasma, and etching a second portion of the silicon nitride layer with the second plasma.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: January 25, 2005
    Assignee: ProMOS Technologies Inc.
    Inventors: Barbara A. Haselden, John Lee
  • Patent number: 6846699
    Abstract: A method of manufacturing a semiconductor device comprises a step of mounting a semiconductor chip on a wiring substrate having a base substrate on which are formed interconnecting lines; while melting the base substrate, bumps provided to the semiconductor chip are pressed in, and the bumps are electrically connected to the interconnecting lines.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: January 25, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Kazunori Sakurai
  • Patent number: 6841404
    Abstract: A method for determining an optical constant of an bottom antireflective layer formed between a resist film and an underlying substrate in an optical lithography process in a process for fabricating a semiconductor device, the resist film having an absorption coefficient ?? of 1.5 ?m?1 to 3.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: January 11, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Kawamura, Eishi Shiobara
  • Patent number: 6841487
    Abstract: A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an insulation film and a conductive layer are formed successively. On the conductive layer a patterned resist is formed. With the patterned resist used as a mask, the conductive layer is dry-etched. A surface layer of the patterned resist is partially removed. With the patterned resist used as a mask, the insulation film is wet-etched.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: January 11, 2005
    Assignees: Renesas Technology Corp., Ryoden Semiconductor System Engineering Corporation
    Inventors: Kojiro Yuzuriha, Shu Shimizu, Tamotsu Tanaka, Takashi Yano
  • Patent number: 6835668
    Abstract: The invention includes a method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising NO3−, F− and one or more organic acid anions having carboxylate groups. The invention also includes a semiconductor processing method of forming an opening to a copper-containing material. A mass is formed over a copper-containing material within an opening in a substrate. The mass contains at least one of an oxide barrier material and a dielectric material. A second opening is etched through the mass into the copper-containing material to form a base surface of the copper-containing material that is at least partially covered by particles comprising at least one of a copper oxide, a silicon oxide or a copper fluoride. The base surface is cleaned with a solution comprising nitric acid, hydrofluoric acid and one or more organic acids to remove at least some of the particles.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: December 28, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Michael T. Andreas, Paul A. Morgan
  • Patent number: 6835671
    Abstract: A extreme ultraviolet (EUV) mask blank having a reflective stack formed by depositing repeated periods of a silicon layer, a first barrier layer, a molybdenum layer, and a second barrier layer using atomic layer deposition is discussed. Precursors using silane and hydrogen are used to form the silicon layer. The first and second barrier layers are preferably different thicknesses of the same material and can be formed using precursors including diborane and methane. In one embodiment, the molybdenum layer is formed using precursors including hydrogen and molybdenum pentachloride or molybdenum pentaiodide. An EUV mask used to pattern a photoresist layer to form an integrated circuit is manufactured from the EUV mask blank.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: December 28, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Scott Daniel Hector, Bich-Yen Nguyen, Dina H. Triyoso