Abstract: The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown from a seed layer to substantially fill openings in a two layer structure wherein the two layers are independently either dielectric or resist layers. According to one aspect of the invention, first and second resist layers are formed into a dual damascene structure. Copper is grown by plating from the copper seed layer to form copper features that fill the pattern gaps.

Abstract: A method of coating a low dielectric constant material layer wherein the wafer surface is pre-wetted using a solvent to prevent or reduce coating defects is described. A semiconductor substrate is provided wherein a top surface of the semiconductor substrate may have surface defects. A solvent is coated overlying the top surface of the semiconductor substrate. A low dielectric constant material layer is coated overlying the solvent wherein the solvent covers the surface defects thereby preventing defects in the low dielectric constant material layer.

Abstract: A structure includes holes formed in a layer of tape. The holes are aligned over active areas on chips formed in a wafer. A custom vacuum chuck with a plurality of suction ports is aligned on the tape such that the suction ports contact only the tape and not the hole portions. Flats of the custom vacuum chuck are formed so that a perimeter of the flats contacts, and rests on, the tape. In addition, the flats of the custom vacuum chuck are formed so that the flats cover the entire active area on the first surface of each of the chips. Consequently, the combination of the custom vacuum chuck and the single layer of tape form a protective cavity over the active areas of the chips during singulation from the wafer.

Abstract: A semiconductor structure (1), comprising a isolation region (5) formed on a semiconductor material (10). A pillar (15) is formed in the semiconductor material under the isolation region, where the pillar is capped with a first dielectric material (20) to form a void (16).

Abstract: A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.

Abstract: A Silicon On Insulator (SOI) structure and method of producing an SOI structure that can prevent a short circuit between a Local Inter-Connect (LIC) and a well in the SOI structure is disclosed. The SOI structure includes a BOX layer of insulation material formed on a silicon substrate; an SOI layer formed on the BOX layer; a well formed within a device isolation area of the SOI layer such that its lower surface is in contact with the BOX layer; a field oxide film formed on a surface side within the well; a gate line formed across an active area on the SOI layer and a portion on the field oxide film; an N+ type source/drain area formed within the active area along both sides of the gate line to contact its lower surface with the BOX layer; an insulation layer formed on such resultant structure; and an opening part that is formed within the insulation layer.

Abstract: A siloxan polymer insulation film has a dielectric constant of 3.3 or lower and has —SiR2O— repeating structural units. The siloxan polymer has dielectric constant, high thermal stability and high humidity-resistance on a semiconductor substrate. The siloxan polymer is formed by directly vaporizing a silicon-containing hydrocarbon compound expressed by the general formula Si&agr;O&bgr;CxHy (&agr;, &bgr;, x, and y are integers) and then introducing the vaporized compound to the reaction chamber of the plasma CVD apparatus. The residence time of the source gas is lengthened by reducing the total flow of the reaction gas, in such a way as to form a siloxan polymer film having a micropore porous structure with low dielectric constant.

Abstract: Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein. The method may comprise employing an anti reflective coating prior to applying a photo resist coating in a semiconductor manufacturing process. Also disclosed are methodologies for exhausting resist residue during development via a rinsing fluid.

Abstract: The present invention provides a method of forming a dielectric on a semiconductor substrate. A dielectric is grown at a substrate interface in a plurality of increments. Stress is relieved at the dielectric substrate interface between each increment. In another aspect, stress relief is performed by annealing the substrate. The annealing is performed by placing the substrate in an inert environment and by raising the temperature surrounding the substrate.

Abstract: A method for improving a doping profile using gas phase doping is described. In the method, silicon nitride and/or products of decomposition from a silicon nitride deposition are introduced in a process chamber before or during the actual gas phase doping. This allows the doping profile to be significantly improved.

Abstract: The invention provides methods and apparatuses of forming a silicon nitride layer on a semiconductor wafer. A semiconductor wafer is located on a susceptor within a semiconductor processing chamber. A carrier gas, a nitrogen source gas, and a silicon source gas are introduced into the semiconductor processing chamber and a semiconductor wafer is exposed to the mixture of gases at a pressure in the chamber in the range of approximately 100 to 500 Torr.

Abstract: Indium Nitride (InN) and Indium-rich Indium Gallium Nitride (InGaN) quantum dots embedded in single and multiple InxGa1−xN/InyGa1−yN quantum wells (QWs) are formed by using TMIn and/or Triethylindium (TEIn), Ethyldimethylindium (EDMIn) as antisurfactant during MOCVD growth, wherein the photoluminescence wavelength from these dots ranges from 480 nm to 530 nm. Controlled amounts of TMIn and/or other Indium precursors are important in triggering the formation of dislocation-free QDs, as are the subsequent flows of ammonia and TMIn. This method can be readily used for the growth of the active layers of blue and green light emitting diodes (LEDs).

Abstract: A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover, the structure including a fuse region and an RDL/bump/bonding pad region. A composite metal layer is formed over the intermetal dielectric layer. The composite metal layer including a second metal layer sandwiched between upper and lower first metal layers. The upper first metal layer is patterned to form an upper metal layer portion within the RDL/bump/bonding pad region. The second metal layer and the lower first metal layer are patterned: (1) within the RDL/bump/bonding pad region to form an RDL/bump/bonding pad; the RDL/bump/bonding pad having a patterned second metal layer portion/lower first metal portion with a width greater than that of the upper metal layer portion and forming a step profile; and (2) within the fuse region to form the top-metal fuse structure. The RDL/bump/bonding pad structure includes a step profile.

Abstract: N2O is used as the oxidant for forming an ultra-thin oxide (14). The low oxidation efficiency of N2O compared to O2 allows the oxidation temperature to be raised to greater than 850° C. while maintaining the growth rate. A cold wall lamp heater rapid thermal process (RTP) tool limits reaction to the surface of the wafer (10). Hydrogen is preferably added to improve the electrical properties of the oxide (14).

Abstract: Silicon oxide films which are good as gate insulation films are formed by subjecting a silicon oxide film which has been formed on an active layer comprising a silicon film by means of a PVD method or CVD method to a heat treatment at 300-700° C. in a dinitrogen monoxide atmosphere, or in an NH3 or N2H4 atmosphere, while irradiating with ultraviolet light, reducing the hydrogen and carbon contents in the silicon oxide film and introducing nitrogen into the boundary with the silicon film in particular. Furthermore, silicon oxide films which are good as gate insulating films have been formed by subjecting silicon oxide films which have been formed on an active layer comprising a silicon film by means of a PVD method or CVD method to a heat treatment at 300-700° C. in an N2O atmosphere (or hydrogen nitride atmosphere) while irradiating with ultraviolet light, and then carrying out a heat treatment at 300-700° C.

Abstract: Low hydrogen-content silicon nitride materials are deposited by a variety of CVD techniques, preferably thermal CVD and PECVD, using chemical precursors that contain silicon atoms, nitrogen atoms, or both. A preferred chemical precursor contains one or more N—Si bonds. Another preferred chemical precursor is a mixture of a N-containing chemical precursor with a Si-containing chemical precursor that contains less than 9.5 weight % hydrogen atoms. A preferred embodiment uses a hydrogen source to minimize the halogen content of silicon nitride materials deposited by PECVD.

Abstract: A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology.

Abstract: In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the insulative layers sandwiched between layers of metal wiring—in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.

Abstract: A semiconductor device in which an integrated circuit is formed includes a resistance-measurement area with conductive members disposed in at least two different layers, and an electrode pattern. The electrode pattern includes contact plugs that, depending on their alignment, make electrical contact with different conductive members. Contact alignment error is measured by measuring the electrical resistance between a pair of electrodes in the electrode pattern.

Abstract: A method of forming a film having enhanced reflow characteristics at low thermal budget is disclosed, in which a surface layer of material is formed above a base layer of material, the surface layer having a lower melting point than the base layer. In this way, a composite film having two layers is created. After reflow, the surface layer can be removed using conventional methods.