Abstract: In a method of manufacturing a semiconductor device of the invention, a substrate insulating film 102 is formed on a semiconductor substrate 100, a barrier layer 104 is formed on the substrate insulating film, an Al—Cu interconnection layer 106 is formed on the barrier layer by sputtering under a condition that the nitrogen concentration in the atmosphere in the sputtering deposition chamber is higher than 12 ppm but lower than 1000 ppm, and then an anti-reflective film 108 is formed on the Al—Cu interconnection layer.

Abstract: A process of making an electrical coupling stack is disclosed. A conductive structure is coupled to a substrate. The coupling includes a crystalline salicide first structure above the conductive structure, a nitrogen-containing amorphous salicide second structure above the crystalline salicide first structure, and a refractory metal third film above the nitrogen-containing amorphous salicide second structure. Processing includes depositing a refractory metal silicide first film over the conductive structure, depositing a refractory metal nitride second film over the refractory metal silicide first film, and depositing the refractory metal third film over the refractory metal nitride second film. Thermal processing is carried out to achieve the electrical coupling stack.

Abstract: An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode (9; see FIGS. 31 and 32) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film (57) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).

Abstract: Embodiments of the present invention relate to a process for filling a trench structure of a semiconductor device to prevent formation of voids in the trench structure so as to minimize current leakage and provide excellent electrical properties. In one embodiment, a process for filling a trench of a semiconductor device comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming an oxide layer on the silicon nitride layer; partially removing the oxide layer, the silicon nitride layer and the semiconductor substrate to form at least one trench; forming a sacrificial oxide layer on sidewalls of the trench; removing the sacrificial oxide layer; performing an etching procedure to remove portions of the silicon nitride layer protruding from the sidewalls of the trench so as to form substantially even sidewalls of the trench; and forming a trench-fill layer to fill the trench and deposit on the oxide layer.

Abstract: A method of forming a top oxide layer of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include forming an in situ steam generation (ISSG) top oxide layer 208 from a charge storing dielectric layer 206 by reacting hydrogen and oxygen on a wafer surface (step 102) and depositing a conductive gate layer 210 (step 104). An ISSG top oxide layer 208 may be of higher quality and formed with a smaller thermal budget than conventional approaches.

Abstract: In a method of manufacturing a semiconductor device, after a lateral growth region 107 is formed by using a catalytic element for facilitating crystallization of silicon, the catalytic element is gettered into a phosphorus added region 108 by a heat treatment. Thereafter, a gate insulating film 113 is formed to cover active layers 110 to 112 formed, and in this state, a thermal oxidation step is carried out. By this, the characteristics of an interface between the active layers and the gate insulating film can be improved while abnormal growth of a metal oxide is prevented.

Abstract: The present invention relates to a method of protecting a fresh metal surface, preferably copper, after a metal deposition step. The metal deposition is preferably part of single or dual damascene process. The metal surface is treated with an amine, preferably BTA, to form a metal complex that is a hydrophobic monolayer and prevents the underlying metal from reacting to form oxides that can degrade device performance. The amine can be applied in various ways including dipping, spraying, spin coating, and by a CVD method. The sacrificial protective layer can remain on the substrate during a storage period of up to hours or days before it is removed in a subsequent chemical mechanical polish step. The use of a sacrificial protective layer improves throughput in a damascene process by allowing long queue times between metal deposition and CMP which gives more flexibility to production flow and reduces cost.

Abstract: A semiconductor structure (1), comprising a isolation region (5) formed on a semiconductor material (10). A pillar (15) is formed in the semiconductor material under the isolation region, where the pillar is capped with a first dielectric material (20) to form a void (16).

Abstract: A method for forming a gate electrode comprising the following steps. A substrate having a high-k gate dielectric layer formed thereover is provided. A gate layer is formed over the high-k gate dielectric layer. A gate ARC layer is formed over the gate layer. The gate ARC layer and the gate layer are patterned to form a pattern gate ARC layer and a patterned gate layer. The high-k gate dielectric layer not under the patterned gate layer is partially etched and a smooth exposed upper surface of the patterned gate layer is formed. The partially etched high-k gate dielectric layer portions not under the patterned gate layer are removed to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.

Abstract: An exemplary embodiment of the present invention includes a method for forming a programmable cell by forming an opening in a dielectric material to expose a portion of an underlying first conductive electrode, forming a recessed chalcogenide-metal ion material in said opening and forming a second conductive electrode overlying the dielectric material and the chalcogenide-metal ion material. A method for forming the recessed chalcogenide-metal ion material comprises forming a metal material being recessed approximately 10-90%, in the opening in the dielectric material, forming a glass material on the metal material within the opening and diffusing metal ions from the metal material into the glass material by using ultraviolet light or ultraviolet light in combination with a heat treatment, to cause a resultant metal ion concentration in the glass material.

Abstract: This invention provides a method to improve the adhesion between dielectric material layers at the interface thereof, during the manufacture of a semiconductor device. The first step is to form a SiC-based dielectric material layer over a substrate. The SiC-based dielectric material layer is treated by oxygen plasma. A second layer of dielectric material is formed over the SiC-based dielectric material layer.

Abstract: A method of controlling a negative differential resistance (NDR) element is disclosed, which includes altering various NDR characteristics during operation to effectuate different NDR modes. By changing biasing conditions applied to the NDR element (such as a silicon based NDR FET) a peak-to-valley ratio (PVR) (or some other characteristic) can be modified dynamically to accommodate a desired operational change in a circuit that uses the NDR element. In a memory or logic application, for example, a valley current can be reduced during quiescent periods to reduce operating power. Thus an adaptive NDR element can be utilized advantageously within a conventional semiconductor circuit.

Abstract: An edge-coupled photodetector, especially a compound semiconductor edge-coupled photodetectors, has a light funnel integrated right in front of the coupling aperture for enhancing the optical coupling efficiency. The light funnel is formed utilizing either a wet etched, crystallographically defined semiconductor slope or a dry etched, resist-profile-defined semiconductor slope covered by the planarized dielectrics. The funnel internals can be partially or fully metallized for total mirror reflection. The lightwave entering the funnel and propagating along the optical axis converges through mirror reflection or total internal reflection. Through such an invention, the edge-coupled photodetector can have both high operation speed and high quantum efficiency with enlarged alignment tolerance.

Abstract: The present invention provides a method for determining resist trim times in an etch process. In one embodiment of the invention, the method for determining resist trim times includes obtaining resist profile data and critical dimension (CD) data of a patterned resist layer using a scatterometer, in a step 520, and then obtaining an estimated trim time of the patterned resist layer using the resist profile data and critical dimension data, in steps 530-550.

Abstract: A method of testing/stressing a charge trapping device, such as a negative differential resistance (NDR) FET is disclosed. By operating/stressing a charge trap device during/after manufacture, a distribution of charge traps can be altered advantageously to improve performance.

Abstract: A method for activating implanted dopants in a semiconductor substrate to form shallow junctions comprises the steps of: maintaining gas pressure in the processing chamber at a level significantly lower than atmospheric pressure, providing a flow of a carrier gas into the processing chamber, subjecting the substrate to a temperature treatment process, and introducing oxygen into the processing chamber during all or part of the temperature treatment process.

Abstract: A composite layer of low k silicon oxide dielectric material is formed on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon. The composite layer of low k silicon oxide dielectric material exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines, deposition rates in other regions comparable to standard k silicon oxide, and reduced via poisoning characteristics. The composite layer of low k silicon oxide dielectric material is formed by depositing, in high aspect ratio regions between closely spaced apart metal lines, a first layer of low k silicon oxide dielectric material exhibiting void-free deposition properties until the resulting deposition of low k silicon oxide dielectric material reaches the level of the top of the metal lines on the oxide layer.

Abstract: Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO2 on a top surface of a silicon wafer and a trench layer of SiO2 on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.

Abstract: A method of manufacturing a semiconductor device, in which a surface (1) of a semiconductor body (2) is provided with a first metallization layer comprising conductor tracks (3, 4), among which a number having a width w an a number having a greater width. On this structure an insulating layer (5) is deposited by means of a process in which the thickness of the formed insulating layer (5) is dependent on the width of the subjacent conductor tracks (3, 4), after which a capping layer (6) is deposited on the insulating layer (5). Then the silicon oxide layer is planarized by means of a polishing process. In this method, the conductor tracks having a width greater than w are split up into a number of parallel strips (10) having a width w, which strips are locally connected to one another.

Abstract: Using deuterium oxygen during stream oxidation forms an oxidizing vapor. Since deuterium is chemically similar to hydrogen, the oxidation process takes place normally and the silicon-silicon oxide interface is concurrently saturated with deuterium. Saturating the interface with deuterium reduces the interface trap density thereby reducing channel hot carrier degradation.