Abstract: The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NH3 diluted with N2, discontinuing the plasma and flow of NH3 and N2, pumping out the chamber; introducing trimethylsilane, NH3 and He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 Å to about 800 Å. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

Abstract: A method of etching nitride over oxide is provided for the formation of vertical profile nitride spacers with high uniformity while maintaining the integrity of underlying thin oxide layers. The method includes providing a first gas flow including a first fluorocarbon and a second fluorocarbon at a first ratio, applying a first quantity of power to the first gas flow to create a first plasma, etching a first portion of a silicon nitride layer with the first plasma, providing a second gas flow including the first fluorocarbon and the second fluorocarbon at a second ratio greater than the first ratio, applying a second quantity of power to the second gas flow to create a second plasma, and etching a second portion of the silicon nitride layer with the second plasma.

Abstract: In the method for determining a preceding wafer, at least one semiconductor wafer is determined as a preceding wafer among a plurality of semiconductor wafers constituting one lot. The preceding wafer is then subjected to a given process among a plurality of processes for fabrication of a semiconductor device. The determination of the preceding wafer is based on processing results of an upstream process among the plurality of processes performed for the plurality of semiconductor wafers prior to the given process. After examination of processing results of the given process on the preceding wafer, the given process is performed for the plurality of semiconductor wafers other than the preceding wafer.

Abstract: A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

Abstract: The invention includes semiconductor processing methods, including methods of forming capacitors. In one implementation, a semiconductor processing method includes providing a semiconductor substrate comprising a layer comprising at least one metal in elemental or metal alloy form. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. At least a portion of the layer is etched in a halogenide, ozone and H2O comprising ambient.

Abstract: A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer of densified dielectric material over the remainder of the underlying layer of low k dielectric material, forming a second layer of low k dielectric material over the layer of densified dielectric material, and treating this second layer of low k dielectric material to form a second layer of densified dielectric material over the second layer of low k dielectric material. The layer or layers of densified dielectric material formed from the low k dielectric material provide mechanical support and can then function as etch stop and mask layers for the formation of vias and/or trenches.

Abstract: Methods of forming a metal layer in integrated circuit devices using selective electroplating in a recess are disclosed. In particular, a recess is formed in a surface of an insulating layer. The recess has a side wall inside the recess, a bottom inside the recess, and an edge at a boundary of the surface of the insulating layer and the side wall. A selective electroplating mask is formed on the side wall to provide a covered portion of the side wall and an exposed portion of the side wall. The exposed portion of the side wall can be electroplated with a metal. Related conductive contacts are also disclosed.

Abstract: An insulation film is formed on a semiconductor substrate by vaporizing a silicon-containing hydrocarbon compound to provide a source gas, introducing a reaction gas composed of the source gas and an additive gas such as an inert gas and oxidizing gas to a reaction space of a plasma CVD apparatus, and depositing a siloxan polymer film by plasma polymerization at a temperature of −50° C.-100° C. The residence time of the reaction gas in the reaction space is lengthened by reducing the total flow of the reaction gas in such a way as to form a siloxan polymer film with a low dielectric constant such as 2.5.

Abstract: A trench capacitor is formed with an insulation collar. After the formation of the trench, firstly an insulating layer is deposited, from which layer the insulation collar will be subsequently formed. Afterward, the trench is partly filled with a sacrificial filling material and a thin patterning layer is deposited thereon. Spacers are formed from that layer and cover the insulating layer in the upper region of the trench. Afterward, the sacrificial filling material and the insulating layer are completely removed in the lower region of the trench. As a result, the insulation collar is produced in the upper region of the trench.

Abstract: The present invention is related to a method for forming a hydrogen barrier layer capable of protecting a bottom structure from damages occurring due to hydrogen produced during a semiconductor device fabrication. The method includes the steps of: forming a hafnium vanadium oxide (HfVOx) layer on a substrate structure providing a predetermined semiconductor device structure, the HfVOx layer being used as a hydrogen diffusion barrier layer; and forming an insulation layer on the HfVOx layer.

Abstract: A method and system for providing a contact hole between structures for a semiconductor device is disclosed. The method and system comprises etching a resist material on the semiconductor device to expose a surface of the structures; providing an implant to the surface of the structures; and removing the resist material from a gap between the structures. The method and system includes annealing the semiconductor device to cause the implant to adhere to the treated surface; and providing dielectric material within the gap. Finally, the method and system includes etching the contact hole in the gap between the structures. The contact hole can then be etched without damaging the structures. Accordingly, by providing an implant treated surface and then providing an anneal process the implant is bonded to the appropriate portion of the semiconductor structure.

Abstract: A method for improving the coating capability of low dielectric layer is disclosed. The method includes steps of an etching stop layer is deposited a semiconductor substrate, an adhesion promoter layer is spun-on the etching stop layer. The pre-wetting process being performed on the adhesion promoter layer to enhance the coating capability of the low-k dielectric layer, and thus improve the coating quality through the pre-wetting process of baked adhesion promoter layer before the low-k dielectric layer is applied.

Abstract: A method for forming a contact or via plug is described. A dielectric layer and a patterned photoresist layer are sequentially formed on a substrate. A portion of the exposed dielectric layer is removed to form a first opening. A first liner is formed on the surfaces of the photoresist layer. An anisotropic etching process is conducted using the first liner and the photoresist layer as a mask to remove a portion of the dielectric layer under the first opening to form a second opening incorporating the first opening. A second liner is formed on the photoresist layer covering the first liner. Then, the above etching step is repeated to form a third opening that incorporates the second opening and exposes the substrate. The second liner, the first liner and the photoresist layer are removed, and then a conductive material is filled into the third opening to form a contact or via plug.

Abstract: A method of forming a dielectric layer includes placing a semiconductor wafer in a reaction chamber. Oxygen, hafnium and silicon sources are separately provided to the reaction chamber to react with the wafer. After each source has reacted, a monolayer or near-monolayer film is produced. Each source may also be provided to the reaction chamber a number of times to achieve a film having the desired thickness.

Abstract: Several methods for producing an active region for a long wavelength light emitting device are disclosed. In one embodiment, the method comprises placing a substrate in an organometallic vapor phase epitaxy (OMVPE) reactor, the substrate for supporting growth of an indium gallium arsenide nitride (InGaAsN) film, supplying to the reactor a group-III-V precursor mixture comprising arsine, dimethylhydrazine, alkyl-gallium, alkyl-indium and a carrier gas, where the arsine and the dimethylhydrazine are the group-V precursor materials and where the percentage of dimethylhydrazine substantially exceeds the percentage of arsine, and pressurizing the reactor to a pressure at which a concentration of nitrogen commensurate with light emission at a wavelength longer than 1.2 um is extracted from the dimethylhydrazine and deposited on the substrate.

Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

Abstract: The present invention relates to a method for providing a dielectric film having a low dielectric constant that is particularly useful as an intermetal dielectric layer. The method of the present invention deposits a porous oxide gap fill layer from a process gas of ozone and TEOS. The gap fill layer is deposited over a surface sensitive lining layer (as opposed to a non-surface sensitive layer as is commonly done in the industry) using deposition conditions that maximize the amount of carbon that is incorporated into the gap fill layer and result in a porous silicon oxide film. A typical SACVD ozone/TEOS gap fill layer has a carbon content of about 2-3 atomic percent (at. %). An SACVD ozone/TEOS gap fill layer deposited according to the present, however, has a carbon content of at least 5 at. % and preferably has a carbon content of between about 7-8 at. %.

Abstract: In a method of depositing a titanium oxide layer on a substrate, a substrate is placed on a support in a process zone of a sputtering chamber. A target containing titanium faces the substrate. A sputtering gas containing an oxygen-containing gas, such as oxygen, and a non-reactive gas, such as argon, is introduced into the process zone. A pulsed DC voltage is applied to the target to sputter titanium from the target. The sputtered titanium combines with oxygen from the oxygen-containing gas to form a titanium oxide layer on the substrate. A multiple layer titanium oxide deposition process may also be implemented.

Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

Abstract: A method of manufacturing a semiconductor device comprises preparing a substrate to be treated, and forming an insulation film above the substrate, which includes applying an insulation film raw material above the substrate, the insulation film raw material including a substance or a precursor of the substance, the insulation film comprising the substance, curing the insulation film raw material by irradiating an electron beam on the substrate while heating the substrate in a reactor chamber, changing at least one of parameter selected from the group consisting of pressure in the reactor chamber, temperature of the substrate, type of gas having the substrate exposed thereto, flow rate of gas introduced into the reactor chamber, position of the substrate, and quantity of electrons incident to the substrate per unit time when the electron beam is being irradiated on the substrate.