Patents Examined by Lisa Kilday
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Patent number: 6743715Abstract: A method for forming a gate silicide portion comprising the following steps. A substrate having a gate oxide layer formed is provided. A gate layer is formed over the gate oxide layer. An RPO layer is formed over the gate layer. A patterned photoresist layer is formed over the RPO layer exposing a portion of the RPO layer. The portion of the RPO layer having a patterned photoresist residue thereover. The structure is subjected to a dry plasma or gas treatment to clean the exposed portion of the RPO layer and removing the patterned photoresist residue. The RPO layer is etched using the patterned photoresist layer as a mask to expose a portion of the gate layer. The dry plasma or gas treatment preventing formation of defects or voids in the RPO layer and the poly gate layer during etching of the RPO layer. A metal layer is formed over at least the exposed portion of the gate layer.Type: GrantFiled: May 7, 2002Date of Patent: June 1, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Juing-Yi Cheng, Yu Bin Huang, Yu Hwa Lee, Chin Shiung Ho
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Patent number: 6743646Abstract: One embodiment of the present invention is a method of designing underlying structures in a wafer with pads of varying sizes and varying loading factors, and selecting the design of pads that yield a reflected metrology signal closest to the calibration metrology signal and that meet preset standard planarization characteristics. Another embodiment is a method of designing underlying structures with random shapes of varying sizes and varying loading factors. Still another embodiment is the use of periodic structures of varying line-to-space ratios in one or more underlying layers of a wafer, the periodicity of the underlying periodic structure being positioned at an angle relative to the direction of periodicity of the target periodic structure of the wafer.Type: GrantFiled: October 22, 2001Date of Patent: June 1, 2004Assignee: Timbre Technologies, Inc.Inventors: Nickhil Jakatdar, Xinhui Niu
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Patent number: 6733591Abstract: The subject invention pertains to a method and device for producing large area single crystalline III-V nitride compound semiconductor substrates with a composition AlxInyGa1-x-y N (where 0≦x≦1, 0≦y≦1, and 0≦x+y≦1). In a specific embodiment, GaN substrates, with low dislocation densities (˜107 cm2) can be produced. These crystalline III-V substrates can be used to fabricate lasers and transistors. Large area free standing single crystals of III-V compounds, for example GaN, can be produced in accordance with the subject invention. By utilizing the rapid growth rates afforded by hydride vapor phase epitaxy (HVPE) and growing on lattice matching orthorhombic structure oxide substrates, good quality III-V crystals can be grown. Examples of oxide substrates include LiGaO2, LiAlO2, MgAlScO4, Al2MgO4, and LiNdO2. The subject invention relates to a method and apparatus, for the deposition of III-V compounds, which can alternate between MOVPE and HVPE, combining the advantages of both.Type: GrantFiled: December 12, 2000Date of Patent: May 11, 2004Assignee: University of Florida Research Foundation, Inc.Inventor: Tim Anderson
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Patent number: 6723594Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 &mgr;m2 to about 10 &mgr;m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.Type: GrantFiled: March 4, 2002Date of Patent: April 20, 2004Inventor: Howard E. Rhodes
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Patent number: 6720276Abstract: Methods of forming a spin-on-glass (SOG) layer are disclosed. An SOG layer is formed on an integrated circuit substrate. A first curing process is performed on the SOG layer. Less than all of the SOG layer is removed from the integrated circuit substrate through a mask pattern on the SOG layer to provide a remaining portion of the SOG layer on the integrated circuit substrate. A second curing process is performed on the SOG layer. The remaining portion of the SOG layer is removed to expose the integrated circuit substrate.Type: GrantFiled: January 30, 2002Date of Patent: April 13, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Min-hee Cho, Chang-hyun Cho, Soo-ho Shin, Hong-sik Jeong
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Patent number: 6716769Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.Type: GrantFiled: December 22, 1999Date of Patent: April 6, 2004Assignee: Micron Technology, Inc.Inventors: Thomas A. Figura, Kevin G. Donohoe, Thomas Dunbar
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Patent number: 6709990Abstract: A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a silicon dioxide layer. This silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A second layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.Type: GrantFiled: October 9, 2002Date of Patent: March 23, 2004Assignee: Atmel CorporationInventors: Mark A. Good, Amit S. Kelkar
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Patent number: 6706582Abstract: An impurity ion of a polarity opposite to that of an impurity ion forming an n-type diffusion layer is implanted into a lower portion of the n-type diffusion region in a region, in which n-channel type MISFET is to be formed, vertically with respect to a main surface of a semiconductor to form a first p-type pocket layer. Subsequently, an impurity of a p conduction type is implanted into a region between the n-type diffusion region and the first p-type pocket layer obliquely relative to the main surface of the semiconductor substrate to form a second p-type pocket layer. In this arrangement, the concentration of the impurity ion forming the second p-type pocket layer is made higher than the concentration of the impurity ion used to form the first p-type pocket layer.Type: GrantFiled: May 17, 2002Date of Patent: March 16, 2004Assignee: Renesas Technology CorporationInventors: Youhei Yanagida, Katsuhiko Ichinose, Tomohiro Saito, Shinichiro Mitani
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Patent number: 6706566Abstract: A method is provided for forming a device. The method provides a substrate, and provides a plurality of nanotubes in contact with the substrate. The method comprises depositing metal contacts on the substrate, wherein the metal contacts are in contact with a portion of at least one nanotube. The method further comprises selectively breaking the at least one nanotube using an electrical current, removing the metal contacts, cleaning a remaining nanotube, and depositing a first metal contact in contact with a first end of the nanotube and a second metal contact in contact with a second end of the nanotube.Type: GrantFiled: May 13, 2002Date of Patent: March 16, 2004Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Philip G. Collins, Vincent Stephane Derycke, Richard Martel
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Patent number: 6703327Abstract: An improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.Type: GrantFiled: June 13, 2002Date of Patent: March 9, 2004Assignee: Micron Technology, Inc.Inventors: Richard H. Lane, Phillip G. Wald
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Patent number: 6703250Abstract: A method for automated monitoring and controlling of a semiconductor wafer plasma etching process including collecting data versus time during a plasma etching process the data including information representative of a concentration of at least one pair of reactant and product species present during the course of the plasma etching process; calculating a selected ratio of at least one reactant species and one product species at selected time intervals in the plasma etching process to create real-time concentration ratio data; retrieving model concentration ratio data for the at least one reactant species and one product species for comparison with the real-time concentration ratio data; comparing the model concentration ratio data with the real-time concentration ratio data to determine a difference; and, adjusting at least one plasma process operating parameter to minimize the difference.Type: GrantFiled: February 14, 2002Date of Patent: March 9, 2004Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Hsien-Kuang Chiu
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Patent number: 6703170Abstract: A method and apparatus for reducing loading effects on a semiconductor manufacturing component during an etch process is disclosed. The transmittance associated with a photomask is calculated and the etch process for a material formed on a semiconductor manufacturing component is adjusted based on the transmittance calculated for the photomask.Type: GrantFiled: December 13, 2001Date of Patent: March 9, 2004Assignee: DuPont Photomasks, Inc.Inventor: Massimiliano Pindo
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Patent number: 6693048Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.Type: GrantFiled: March 5, 2002Date of Patent: February 17, 2004Assignee: Micron Technology, Inc.Inventors: Richard H. Lane, Phillip G. Wald
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Patent number: 6683010Abstract: A semiconductor device provides improved performance at high integration levels by utilizing a gate insulation layer formed from silicon-oxynitride which prevents impurities in the doped gate electrode from diffusing into the semiconductor substrate during the fabrication processes. A method for forming the silicon-oxynitride layer utilizes a vertical diffusion furnace to increase productivity and achieve a uniform nitrogen density in the silicon-oxynitride layer. The method includes forming an initial oxide layer on a semiconductor substrate, changing the initial oxide layer into a pure oxide layer, and then changing the pure oxide layer into a silicon-oxynitride layer. The initial oxide layer is formed by loading a semiconductor substrate into a diffusion furnace at a temperature between 550˜750° C., raising the temperature of the substrate to between 700˜950° C., and injecting a mixture of oxygen and nitrogen has into the diffusion furnace.Type: GrantFiled: June 25, 1998Date of Patent: January 27, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Baek-gyun Lim, Eu-seok Kim, Chang-jip Yang, Young-kyou Park
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Patent number: 6677233Abstract: Introduction of a liquefied gas solution for deposition of a material on a semiconductor substrate. The substrate can have a trench etched thereinto with the solution including ions of the material to be deposited in the trench. The substrate can have a barrier layer at its surface prior to introduction of a liquefied gas solution including ions of a metal to be deposited above the barrier. A material layer to be formed on the substrate can be a tantalum barrier, a copper layer or other semiconductor processing feature.Type: GrantFiled: January 2, 2002Date of Patent: January 13, 2004Assignee: Intel CorporationInventor: Valery M. Dubin
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Patent number: 6673725Abstract: The present invention relates to a semiconductor device manufacturing method for forming an interlayer insulating film having a low dielectric constant by coating a copper wiring. The low dielectric constant insulating film is formed by reaction of a plasma of a film-forming gas containing an oxygen-containing gas of N2O, H2O, or CO2, ammonia (NH3), and at least one of an alkyl compound having a siloxane bond and methylsilane (SiHn(CH3)4−n: n=0, 1, 2, 3).Type: GrantFiled: April 30, 2001Date of Patent: January 6, 2004Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.Inventors: Yoshimi Shioya, Kouichi Ohira, Kazuo Maeda
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Patent number: 6673691Abstract: A method of changing the resistance of a perovskite metal oxide thin film device with a resistance-change-producing pulse includes changing the resistance of the device by varying the duration of a resistance-change-producing pulse.Type: GrantFiled: September 26, 2002Date of Patent: January 6, 2004Assignee: Sharp Laboratories of America, Inc.Inventors: Wei-Wei Zhuang, Sheng Teng Hsu
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Patent number: 6673722Abstract: An improved chemical vapor deposition or etching is shown in which cyclotron resonance and photo or plasma CVD cooperate to deposit a layer with high performance at a high deposition speed. The high deposition speed is attributed to the cyclotron resonance while the high performance is attributed to the CVDs.Type: GrantFiled: May 9, 1997Date of Patent: January 6, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 6670289Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized, sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.Type: GrantFiled: May 17, 2002Date of Patent: December 30, 2003Assignee: Micron Technology, Inc.Inventors: Richard H. Lane, Phillip G. Wald
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Patent number: 6670657Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.Type: GrantFiled: January 11, 2002Date of Patent: December 30, 2003Assignee: STMicroelectronics S.A.Inventors: Olivier Menut, Yvon Gris