Abstract: A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.

Abstract: There is disclosed a process for making high performance bipolar and high performance MOS devices on the same integrated circuit die. The process comprises forming isolation islands of epitaxial silicon surrounded by field oxide and forming MOS transistors having polysilicon gates in some islands and forming bipolar transistors having polysilicon emitters in other islands. Insulating spacers are then formed around the edges of the polysilicon electrodes by anisotropically etching a layer of insulation material, usually thermally grown silicon dioxide covered with additional oxide deposited by CVD. A layer of refractory metal, preferably titanium covered with tungsten, is then deposited and heat treated at a temperature high enough to form only titanium disilicide to form silicide over the tops of the polysilicon electrodes and on top of the bases, sources and drains.

Abstract: A nonvolatile trench memory device such as an EEPROM is made by a method which permits an extremely compact and simple configuration due to the use of precise and efficient self-alignment techniques. Oxide-capped polysilicon mesas, formed integrally with the control gates, form the word lines of the memory device, while drain metallization lines contact drain regions of the device and extend over the oxide-capped word lines to form the bit lines. The resulting device is extremely compact, since the self-aligned process permits tighter tolerances and the unique polysilicon mesa/oxide cap construction permits a more compact configuration.

Abstract: Disclosed is a method comprising forming a first electrode by forming a conductive layer on a semiconductor substrate, forming an etching mask on the conductive layer, etching the conductive layer and defining the conductive layer into cell units; and forming a dielectric film and a second electrode or the first electrode. Also disclosed is a method comprising forming a first electrode by forming a conductive structure on a semiconductor substrate, forming an etching mask on the conductive structure and etching the conductive structure; and forming a dielectric film and a second electrode on the first electrode. An insulating layer including pin holes such as a silicon nitride layer is formed on the conductive structure or the conductive layer; which is exposed under an oxidative atmosphere. The surface portion of the conductive structure or conductive layer is oxidized to form silicon oxide islands to be used as an etching mask.

Abstract: An improved method and resulting structures for producing a layered capacitor structure of memory cell of a DRAM device wherein a doped polysilicon spacer operates as a dopant source for an overlying polysilicon layer on the vertical and sharply inclined surfaces.

Abstract: Methods for the production of wiring structures are disclosed which are rendered suitable, particularly for use in semiconductors. An electrically conductive material of a selected class is refilled, in a specified manner and by the bias ECR-CVD system, into the connecting hole positioned on a substrate. This is conducive to voidless refilling of the connecting hole and also to thin lamination of the electrically conductive material on a wiring region.

Abstract: A dynamic random access memory has a plurality of memory cells, each cell is defined by a substrate made of semiconductor material, a capacitor for storing data, a first transistor connected to one side of the capacitor. The first transistor is formed of a thin film transistor, and a second transistor of the memory cell is connected to the other side of the capacitor. By this arrangement, the size of each memory cell is reduced.

Abstract: A method of manufacturing a semiconductor device is manufactured as a MOS-type mask ROM in which the threshold voltage in a transistor used as a memory cell varies from stage to stage by ion implantation. As a result, a period for storing data can be shortened by writing data in the late stage of the manufacturing process, and specified ions are implanted with multi-stage energy with a gate electrode of the transistor covered with an insulating film of a layer insulating film or of a layer insulting film and a protective film to vary the threshold voltage stably.

Abstract: A method for forming a diode provided with electrodes and a semiconductive layer. Such method comprises applying ion beam irradiation to a substrate having a protruding portion at a desired position for monocrystalline diamond formation. In this manner the substrate is and subjected to surface modification thereby effecting a process for diamond crystal growth on the substrate.

Abstract: A method of producing a Schottky junction including a semiconductor substrate and a metal film includes successively producing on a semiconductor substrate a first insulating film, a second film having a different etching speed from that of the first insulating film, and a third insulating film having a different etching speed from that of said second film, exposing a part of the second film by dry etching the third insulating film, etching the second film using the third insulating film as a mask to expose part of the first insulating film, dry etching the first insulating film to expose part of the substrate, and producing a metal film forming a Schottky junction with the substrate on the exposed part of the semiconductor substrate.

Abstract: Disclosed is a semiconductor integrating circuit having stacked capacitor cells. Each of the cells includes an electric charge storage electrode for storing an electric charge, and a capacitor insulation film and opposite plate electrode integrated thereon. The electric charge storage electrode consists essentially of a bottom and a part in at least double frame-like portion or at least one column-like portion and at least one frame-like portion surrounding the column-like portion rising upwardly from the bottom surface. The capacitor deposited film consists of a dielectric material film deposited on all of the bottom plane and all surfaces of the charge storage electrode, and constructs a capacitor in cooperation with the opposite plate electrode. The described method for making a stacked capacitor cell can make it possible to form self-aligned capacitors by repeating a deposition of an oxide film and a conductive film and an anisotropic etching.

Abstract: This invention relates to a pn-junction device, especially a blue light-emitting diode and a method of the manufacturing thereof. The pn-junction is formed between a superlattice region and a n-type semiconductor region, the superlattice region consisting of a plurality of stacked pairs of ZnSe semiconductor layer and acceptor-impurity-doped ZnS.sub.0.12 Se.sub.0.88 mixed crystal semiconductor layer formed on a part of a buffer layer of ZnS.sub.0.06 Se.sub.0.94 etc. which is formed on a crystalline substrate of GaAs etc., the n-type semiconductor region being formed on the part of the buffer layer, where the superlattice is not formed, and the side wall of the superlattice region contiguous to the n-type region to form pn-junction being made clean by etching, so that a pn-junction of n-type semiconductor and p-type semiconductor having high carrier-density resulted.

Abstract: Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. A PIN diode region 14 of the first conductivity type is then implanted in the substrate 10 at the first surface and spaced from the HBT subcollector region 12. Next, an i-layer 16 is grown over the first surface. Next, an HBT base/PIN diode layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12 and the PIN diode region 14. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base/PIN diode layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base/PIN diode layer 22.

Abstract: An integrated EPROM device which can be manufactured using standard high definition photolithographic techniques with unit cells of markedly reduced dimensions as compared to the minimum dimensions that can be achieved with the prior art, has field isolation structures between adjacent cells along rows of the array in the form of continuous isolation strips which extend for the whole column length of the array, thus avoiding the problems associated with photolithographic defining rectangular geometries. The electrical interconnection between the sources of the cells of each row is achieved by a special metal source "line", formed between two adjacent gate lines, using for the purpose a conformally deposited metal layer from which both the drain contacts and these source interconnection metal "lines" are created in a self-alignment way.

Abstract: Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate.

Abstract: The present invention provides improved programmability of antifuse elements by utilizing local enhancement of an underlying diffusion region. During an existing fabrication of a semiconductor device using antifuse elements after the access lines (usually word lines) are formed, a self-aligning trench is etched between two neighboring access lines thereby severing an underlying diffusion region. Following an etch back of the access lines' spacers a low energy, heavy dose implant dopes the exposed edges of the diffusion region resulting from the spacer etch back, as well as the bottom of the trench. An antifuse dielectric is formed followed by placing of a second conductive access line (usually the source lines) thus filling the trench to serve as the programmable antifuse element. The heavily doped areas in the diffusion region will now allow a reduction in programming voltage level, while providing a sufficient rupture of the antifuse dielectric.

Abstract: According to a method for manufacturing a nonvolatile semiconductor memory device, first, a CVD oxidation film is formed in a side wall portion of a floating gate formed on a semiconductor substrate. Then, a thermal oxidation film is formed between said floating gate and said CVD oxidation film by a thermal oxidation method. Additionally, before forming said CVD oxidation film, a thermal oxidation film may be formed in the side portion of said floating gate.

Abstract: The present invention provides a method of manufacturing a nonvolatile semiconductor memory device. In the method of the present invention. Arsenic ions are implanted into an element region of a silicon substrate so as to form a first impurity region. Then, an insulating film is formed on the silicon substrate in the element region, followed by forming a heat resistant film on the entire surface of the silicon substrate. Further, a resist film is formed on the silicon substrate, followed by patterning the resist film to form an opening on at least the first impurity region. After the patterning step, the heat resistant film positioned below the opening of the resist film is removed, followed by implanting phosphorus ions into the substrate using the patterned resist film as a mask so as to form a second impurity region. In the next step, the resist film is removed and, then, annealing is applied with the heat resistant film used as a mask.

Abstract: A semiconductor laser device is disclosed which comprises a semiconductor substrate having a ridge portion, the width of the ridge portion being smaller in the vicinity of the facets than in the inside of the device; a current blocking layer formed on the substrate including the ridge portion; at least one striped groove formed on the center of the ridge portion through the current blocking layer; and a multi-layered structure disposed on the current blocking layer, the multi-layered structure successively having a first current blocking layer, an active layer for laser oscillation, and a second current blocking layer; wherein at least two side grooves are symmetrically formed on both sides of the center region of the ridge portion with the same width as that of the regions thereof near the facets. Also, disclosed is a method for producing the semiconductor laser device.

Abstract: A method of forming a bit line over capacitor array of memory cells includes providing a first layer of polyimide over word lines. Such layer is then patterned and etched to define storage node circuits. A first layer of conductively doped polysilicon is applied over the first layer of polyimide. A second layer of polyimide is applied over the first layer of conductively doped polysilicon. The second layer of polyimide and first layer of polysilicon are etched over the first layer of polyimide to define isolated cell storage nodes. Such can be conducted without any prior patterning or masking of the second layer of polyimide and first layer of polysilicon. A third layer of polyimide is provided atop the wafer over the isolated cell storage nodes. The third and first layers of polyimide are etched to define bit line contacts. Insulating spacers are provided about the periphery within the bit line contacts. Conductive material is deposited to provide conductive material pillars within the bit line contacts.