Abstract: A high band-gap opto-electronic device is formed by epitaxially growing the device section in a lattice-matched (Al.sub.x Ga.sub.1-x).sub.y In.sub.1-y P-GaAs system. The band-gap of the epitaxial layer increases with x. Instead of growing the device section directly on the GaAs substrate, a layer of (Al.sub.x Ga.sub.1-x).sub.y In.sub.1-y P, graded in x and in temperature while maintaining substantially y=0.5, is grown as a transitional layer. The high band-gap device structures include homojunctions, heterojunctions and particularly a separate confinement quantum well heterostructures. Various embodiments of the invention include devices on absorbing substrates and on transparent substrates, and devices incorporating strained-layer superlattices.

Abstract: A method of forming a capacitor in semiconductor water processing comprising the following steps: a) providing a conductively doped first layer of polysilicon atop a silicon wafer to a first thickness; b) depositing an undoped second layer of polysilicon over the conductively doped first layer of polysilicon to a second thickness, the layer of undoped polysilicon being deposited at a deposition temperature of at least 590.degree. and having an upper surface; c) impinging laser energy onto the upper surface of the second polysilicon layer at a laser fluence of 0.3 J/cm.sup.2 or greater to roughen the upper surface and thereby increase the capacitance of the second polysilicon layer; d) patterning and etching the first and second polysilicon layers to define a lower capacitor plate; e) providing a layer of capacitor dielectric atop the roughened second polysilicon layer upper surface; and f) providing a layer of conductive material atop the capacitor dielectric to define an upper capacitor plate.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: A process for manufacturing a ferroelectric memory array of stacked-cell design that can be operated in both dynamic and nonvolatile modes. The process deviates from conventional stacked cell array processing at the storage node plate formation stage. A storage node polysilicon layer is conformally deposited, while being in-situ conductively doped, to a depth greater than that necessary to completely fill inter-wordline gaps (if not already planarized) and inter-bitline gaps (in the case of a buried digit line process flow). The storage-node poly layer is then planarized to a level at which poly still covers the entire array. Next, a barrier layer of a refractory metal (e.g., platinum) or of a refractory metal silicide is created on top of the planarized storage-node poly layer. A disposable polyimide layer, which is deposited on top of the barrier layer, is patterned during the same step in which the storage node contact layer and barrier layer are patterned.

Abstract: Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Abstract: A memory cell comprises a semiconductor pillar comprising an inversion layer formed on a side wall of the pillar. A conductive capacitor of the memory cell comprises a first electrode formed by the inversion layer. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region comprising the inversion layer. The gate is coupled to a control line partially overlying a top end of the pillar.

Abstract: In the process described, the electronic circuits (2) for the signal processing and the sensor structures to which they are coupled are manufactured side by side on the common substrate (1). The process is characterized by the following steps: manufacture of the electronic circuits on the substrate (1) by known semiconductor techniques; application to the surface of the substrate (1) of a galvanic electrode layer (7), which may or may not be structured; application on the substrate surface containing the electrode layer of an X-ray resist layer (8), the thickness of which corresponds to a characteristic height of the sensor structures to be produced; production of negatives (10, 11) of the sensor structures in this resist layer (8) by X-ray lithography: galvanic deposition of a metal (12, 13) or a metal alloy in the negatives (10, 11) of the sensor structures using the galvanic electrode layer; division of the substrate with the sensor structures applied thereto into separate functional units or chips.

Abstract: A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor begins by selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices. A gate dielectric layer is formed on the substrate in the device areas. A relatively thick first layer of polysilicon is deposited on the field oxide areas and the device areas. Portions of the first polysilicon layer is removed while leaving portions thereof for the gate structure in the device areas, and portions over the field oxide areas. A first insulator layer composed at least in part of silicon nitride is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a second polysilicon layer over the device and field oxide areas.

Abstract: A method of manufacturing a semiconductor device comprises the steps of preparing a semiconductor substrate, forming a field oxide layer for isolation between active areas, forming a diffusion layer in a surface of the semiconductor substrate, depositing a first insulating interlayer on the semiconductor substrate, forming a W-polycide layer including As on the first insulating interlayer selectively, depositing a second insulating interlayer on the first insulating interlayer and on the W-polycide layer, forming a first contact hole with a shallow depth on the W-polycide layer and a second contact hole with a deep depth on the diffusion layer, depositing a W layer in only the second contact hole by selective CVD so as not to form a step with the second insulating interlayer and, contacting the W-layer and the polycide layer by forming a wiring layer on the surface of the second insulating layer.

Abstract: For manufacturing an electrically conductive tip composed of a doped semiconductor material, a mask layer is produced on a substrate composed of the semiconductor material. This mask layer contains a material at least at its surface and directly on the substrate whereon the semiconductor material does not grow in a selective epitaxy. An opening wherein the surface of the substrate lies exposed is produced in the mask layer. The electrically conductive tip is produced by a selective epitaxy on the exposed surface of the substrate such that the layer growth in the direction parallel to the surface of the substrate is lower than in the direction perpendicular to the surface of the substrate.

Abstract: A method of manufacturing a bipolar transistor includes selectively removing portions of a semiconductor layer on a semiconductor substrate photolithographically to form an isolation trench and first and second mesa regions surrounded and separated by the trench, and forming a first insulation film on inner walls of the trench. Then, a second insulation film is formed on the upper surfaces of the mesa regions, and a first polycrystalline silicon layer is formed on the first insulation film. Polycrystalline silicon is selectively grown from the first polycrystalline silicon layer onto the second insulation film to form a second polycrystalline silicon layer while leaving exposed a portion of the second insulation film.

Abstract: A three level mask structure is formed on a wafer. The top layer of the mask structure has an opening that defines an etch area. The middle layer of the mask structure is etched through the opening in the top layer. This opening in the middle layer defines a gate deposition area. The layer adjacent to the wafer is etched, using the opening in the middle mask layer to define the etch area, until the etching undercuts the middle layer by a predetermined amount. The opening in the layer adjacent to the wafer is used to define an etch area on the wafer. The wafer is etched to form source and drain areas. Gate material is deposited onto the wafer using the opening in the middle layer to determine the deposition area. The mask structure is then removed.

Abstract: In a method of fabricating a semiconductor device according to the present invention, a semiconductor film is formed on a substrate, and an insulator film is formed so as to cover the semiconductor film. Then, a dopant source is arranged on the insulator film and then, a region for electrical contact is irradiated with a high-energy beam through the dopant source. Consequently, the insulator film and the semiconductor film in the irradiated region are melted, to form a polycrystalline contact region having impurities supplied from the dopant source doped therein. Thus, the high-energy beam is irradiated to the region for electrical contact through the dopant source to form the polycrystalline contact region, thereby to make it possible to omit the patterning process such as etching processing for providing a contact hole.

Abstract: A method for fabricating a buried zener diode concurrently with other semiconductor devices on a large scale semiconductor wafer includes utilizing a composite mask to define one or more stable buried zener diodes, one or more additional semiconductor devices, and a number of isolation regions. After applying a screen oxide over selected portions of the semiconductor wafer, subsequent ion implantation steps and additional masking steps concurrently form the stable buried zener diode along with additional and different semiconductor devices utilizing conventional ion implant bi-polar processing techniques.

Abstract: A method for manufacturing a semiconductor device by (i) depositing a first insulating layer over a semiconductor substrate having a polysilicon gate, and then opening a first contact hole so as to form a first insulating film, (ii) depositing a second polysilicon layer over the semiconductor substrate including the first contact hole, and then patterning the same so as to form a second polysilicon film, (iii) depositing a second insulating film over the semiconductor substrate including the second polysilicon film, and then opening a second contact hole so as to form a second insulating film, (iv) depositing a third polysilicon layer over the semiconductor substrate including the second contact hole, and then patterning the same as to form a third polysilicon film as a capacitor bottom electrode, (v) implanting ions in the second polysilicon film in a region other than a capacitor formation region so as to form a source/drain region, (vi) depositing a third insulating layer over the whole surface, and then o

Abstract: Disclosed is a process for fabricating a semiconductor wafer to form a memory array and peripheral area, where the array comprises nonvolatile memory devices employing floating gate transistors and the peripheral area comprises CMOS transistors. A first layer of conductive material is applied atop insulating layers. A dielectric layer is applied atop the first conductive layer for use in floating gate transistors within the array. The dielectric layer and first conductive material are etched from the peripheral area, leaving patterned dielectric material and first conductive material in the array. A second layer of conductive material is applied atop the wafer to cover the peripheral area and dielectric layer of the array. The conductive and dielectric materials of the array are patterned and etched separately from the patterning and etching of conductive material of each of the first and second conductivity type CMOS transistors of the peripheral area.

Abstract: A method for cleaving semiconductor wafers, or segments thereof, which comprises placing the wafer, provided with scribe lines defining the planes where cleaving is to take place, inbetween a pair of flexible transport bands and guiding it around a curved, large radius surface thereby applying a bending moment. With a moment of sufficient magnitude, individual bars are broken off the wafer as this is advanced, the bars having front-and rear-end facets. On cleaving, each bar, while still pressed against the curved surface, is automatically separated whereby mutual damage of the facets of neighboring bars is prevented. For further handling, e.g. for the transport of the bars to an evaporation station for passivation layer deposition, provisions are made to keep the bars separated. Cleaving and the subsequent passivation coating can be carried out in-situ in a vacuum system to prevent facet contamination prior to applying the passivation.

Abstract: A thyristor having low-reflection light-triggering structure. In a light-triggerable thyristor, pyramidal depressions are formed in a simple manner by a preferred etching method, being formed in the region of the photon entry face in order to produce a low-reflection light-triggering structure. Incident light is absorbed in the pyramidal depressions largely independent of the wavelength of the incident light and nearly completely. The low-reflection light-triggering structure thereby produced can be formed with relatively little outlay. This is especially true when a defined overhead ignition voltage is simultaneously set by the pyramidal depressions.

Abstract: This invention provides a step cut type insulated gate static induction tsistor having a first main electrode formed in one major surface of a semiconductor substrate, a second main electrode formed in a bottom portion of a U-shaped groove formed in one major surface of a semiconductor substrate, a control electrode formed on a side wall of the U-shaped groove and consisting of a thin insulating film and a polysilicon layer, and a low-resistance electrode of a refractory metal layer or a refractory metal silicide layer formed in at least part of the side wall of the polysilicon layer of the control electrode.

Abstract: An ultra-high-speed photoconductive device is described which comprises a homoepitaxial semi-insulating III-V layer, or body, upon which ohmic/conductive contacts, or strips, separated by a small gap, are formed. The semi-insulating body, or layer, is produced by low temperature growth of III-V compounds by MBE. In a GaAs embodiment, the layer is grown under arsenic stable growth conditions, at a substrate temperature preferably in the range of 150.degree. to about 300.degree. C.