Abstract: A dynamic random access memory (DRAM) storage cell having a storage contact capacitor comprising a tungsten and TiN storage node capacitor plate and the method for fabricating the same. At least a portion of the storage node capacitor plate is formed vertically in the DRAM. The TiN is controllably etched to increase the area of the storage node capacitor plate. An upper poly layer functions as the cell plate and is insulated from the storage node capacitor plate by a dielectric layer.

Abstract: The method for fabrication of openings in semiconductor devices to improve metal step coverage includes forming an active region over a substrate. A metal oxide layer is then formed over the source/drain region. An insulating layer is formed over the metal oxide layer. A photoresist layer is formed over the insulating layer, and patterned to form an opening, exposing a portion of the insulating. The insulating layer is then etched to expose a portion of the metal oxide layer. The photoresist layer is removed and the insulating layer is reflowed so as to form rounded corners at the opening of the insulating layer. The exposed portion of the metal oxide layer is removed to expose a portion of the active region.

Abstract: A process for forming a buried contact (50) in a semiconductor device (20) which avoids etch damage to the substrate and forms a self-aligned, low resistance contact to a silicon substrate (22) is provided. After forming a contact opening (32) through overlying insulating and conducting layers (24, 28,30), a silicide region (40) is formed in the substrate at the contact surface (34) exposed by the contact opening (32). A refractory metal silicide which provides high etching selectivity to polysilicon is formed in the substrate at the contact surface (34) by either a blanket deposition of a refractory metal into the contact opening (32), or alternatively, by a selective deposition process using contact surface (34) as a nucleation site. In a preferred embodiment, a cobalt or tantalum silicide region (40) is formed in the substrate at the contact surface (34) and a conductive layer (42) is deposited and etched to form an interconnect (48) contacting the silicide region (40).

Abstract: The invention comprises processes and heterostructure products defining silicon on insulator waveguides (80, 88, 90, 106, 112, 120, 122) that are suitable for use with light in the 1.3, 1.6 .mu.m or greater wavelengths. Silicon is deposited on an insulator layer 12 on a crystalline substrate 10 and grown or regrown in crystalline form. The silicon is then etched or formed into a waveguide structures.

Abstract: A process for the fabrication of an EEPROM structure requiring only two poly layers that utilize hot electrons from the substrate for programming and poly-to-poly electron tunneling for erasure. The structure is advantageously utilized in an Ultra Violate Light Erasable PROM.The process results in a structure that allows programming and erasure by electron tunneling only.

Abstract: A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).

Abstract: A method for making a sense amplifier capable of achieving high-speed sensing operation as well as incurring less influence from electrostatic capacitance of bit lines in a high-integration semiconductor memory (DRAM) device is disclosed. The DRAM device includes a plurality of word line pairs and bit line pairs, and a plurality of memory cell arrays with a plurality of memory cells, and further includes discrete sense amplifier circuits connected to each of the memory cell arrays, common sense amplifier circuits coupled between the discrete sense amplifiers, and separation circuits controlled by a given control signal and connected between the discrete sense amplifier circuits and common sense amplifier circuits.

Abstract: The present invention discloses a logic semiconductor device having a non-volatile memory in which a memory cell portion and a logic circuit portion are formed on a single semiconductor substrate, and a floating gate of the memory cell portion and a gate of the logic circuit portion are made of different materials, and a method of manufacturing the same.

Abstract: A semiconductor-based radiation-detector element particularly adapted to neutron detection, and the method for making the same, in which a high sensitivity single-crystal semiconductor substrate has diffused therein at-least-one region of .sup.3 He gas, which remain resident therein, whereby, upon application of an inverse bias to the junction in the semiconductor substrate, the colliding of incident neutrons with the resident .sup.3 He gas results in a reaction which produces hole-electron pairs in the depletion layer within the semiconductor, those hole-electron pairs producing output electrical pulses which appear at the output terminals of the detector for utilization by detection and measuring apparatus connected to the semiconductor-based radiation-detector element.

Abstract: Preferred embodiments include a microstrip patch antenna (38) which also acts as the resonator for an oscillator powered by IMPATT diodes (34, 36); this forms a monolithic transmitter (30) for microwave and millimeter wave frequencies.

Abstract: A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of a polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.

Abstract: The present invention relates to an integrated circuit which includes complementary MOS transistors (e.g., a CMOS circuit), an EEPROM, and to a method of making the integrated circuit. The EEPROM is incorporated in the circuit in such a manner that it does not adversely affect the high performance, low voltage operation of the CMOS circuit. Also, the EEPROM is designed so that it is programmable at a low voltage which is compatible with the low voltages typically used with the CMOS circuit. The EEPROM includes a floating gate and a control gate which have a large area of overlap so as to provide a high capacitance therebetween. This provides a high ratio (e.g., about two or greater) of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance to provide the EEPROM with the low voltage operation. To make the integrated circuit, standard CMOS process steps using design rules of about two microns or less are used to make the MOS transistors.

Abstract: A method of producing a semiconductor light emitting device includes forming a stripe-shaped mesa on a surface of a semiconductor substrate; epitaxially growing a multiple layer structure including at least a first cladding layer, an active layer, a second cladding layer, and a cap layer so that the active layer and cap layer have mesas corresponding to the mesa of the substrate; depositiong photoresist on the cap layer to form a flattened surface; removing the photoresist to expose the mesa of the cap layer; removing a portion of the cap layer using the photoresist remaining on the cap layer as a mask to make the surface of the cap layer approximately flat; depositing a thin film to be used as a mask for proton or ion bombardment on the cap layer and on the remaining photoresist; removing the remaining photoresist and the thin film on the remaining photoresist; and bombarding the cap layer with protons and ions using the remaining thin film on the cap layer as a mask to produce higher resistivity regions adj

Abstract: This is an SRAM cell and the cell can comprise: two NMOS drive transistors; two PMOS load transistors; first and second bottom capacitor plates 50, 52, with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20, 26 over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors, whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.

Abstract: According to the structure of the invention, an AlGaInP cladding layer of one conductive type, an active layer, and an AlGaInP cladding layer of other conductive type greater in thickness in stripes are formed on a GaAs substrate, and an insulating film, AlGaInP or amorphous layer smaller in refractive index than the AlGaInP cladding layer are formed at both sides of the stripes, wherein the light can be confined and guided also in the direction parallel to the active layer, and the light can be index-guided both in the direction parallel to the active layer and in the direction vertical thereto, so that a laser having an extremely smaller astigmatism may be presented. What is more, the current blocking layer disposed at the outer side of the insulating film, AlGaInP or amorphous layer is high in thermal conductivity, and the heat generated in the vicinity of the active layer may be efficiently released.The invention also relates to the method of fabricating the laser composed in such structure.

Abstract: A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.

Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked H-Cell (SHC). The SHC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SHC is made up of a polysilicon storage node structure having a H-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SHC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an H-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.

Abstract: A method for forming a field emission device. The method includes steps which utilize sidewall spacer formation techniques. The sidewall spacer(s) are employed to properly orient the various conductive elements of the field emission device.

Abstract: Highly doped N- and P-type wells (16a, 16b) in a first silicon layer (16) on an insulator layer (14) of a SIMOX substrate (10). Complementary MOSFET devices (52,54,58,62) are formed in lightly doped N- and P-type active areas (22a, 22b) in a second silicon layer (22) formed on the first silicon layer (16). Adjacent active areas (22a, 22b) and underlying wells (16a, 16b) are isolated from each other by trenches (36,78) filled with a radiation-hard insulator material. Field oxide layers (42,64) are formed of a radiation-hard insulator material, preferably boron phosphorous silicon dioxide glass, over the surface of the second silicon layer (22) except in contact areas (68) of the devices (52,54,58,62). The devices (52,54,58,62) are formed in the upper portions of the active areas (22a, 22b), and are insensitive to the interfacial states of the SIMOX substrate (10).

Abstract: Improved light output from LED's or the like are obtained by modifying the combined thickness dimensions of a transmissive diffusion mask layer and anti-reflection coating layer at the periphery of the window forming the light-emitting region.