Abstract: A Schottky diode has a metal lead electrically connected to the Schottky contact layer wherein the metal lead is metallurgically bonded to the diode for increased reliability, the diode having a Ta--Si--N barrier layer.

Abstract: A process for separating image sensor dies and the like from a wafer in which pairs of separation grooves separating each row of dies are formed in the active side of the wafer, with the tab between each groove pair being substantially equal to the width of the dicing blade, cutting a single bottom groove in the inactive side of the wafer opposite to and spanning each pair of separation grooves, and aligning the dicing blade with the midpoint of the wall of one groove in each pair of grooves so as to cut between the rows of dies. In a second embodiment, a two-pass separation process is enabled in which the tab between separation grooves is slightly larger than the width of the dicing blade, with the dicing blade first aligned with the midpoint of one separation groove to cut one row of dies from the wafer together with part of the tab, with the blade realigned with the midpoint of the other separate groove to cut a second row of dies and the remainder of the tab.

Abstract: A method of manufacturing a semiconductor device, such as a semiconductor diode laser, is set forth to form a mesa and current blocking structure on either side of the mesa. In this technique a lift-off step is used to form a contact layer as a direct result of removing semiconductor layers. This is accomplished by using a selective etchant that removes overlying layers, but does not remove a subjacent layer which may be the contact layer. As a result, the growing process is economized by an inexpensive method having a high yield.

Abstract: A semiconductor contact system is formed by inductively coupling an ohmic electrode, such as a metal, to a semiconductor region by means of an intervening diamagnetic boride glass, which necessarily constrains most electric current to prevail along the uniaxial normal to the semiconductor contact. The low permeability of the diamagnetic boride glass results in a low resistance to direct-current electricity along the uniaxial displacement axis of the diamagnetic boride glass. The transient time constant associated with the inductor is generally much smaller than the semiconductor device switching times, with the steady-state current being essentially established by the semiconductor resistance so as to result in an ohmic semiconductor contact void any significant rectification effects. An ohmic contact by means of an inductively-coupled electrode is generally independent of the semiconductor conductivity or ionicity.

Abstract: A resist pattern having a prescribed opening is formed over a semiconductor substrate through an insulative layer. A Ti film is formed, by oblique vacuum vapor deposition, on the resist pattern and on part of the area of the insulative layer which constitutes the bottom surface of the resist opening. The insulative film is etched using the Ti film as a mask to form a groove through the insulative layer.

Abstract: A method of fabricating electron field emitters is disclosed. In this method, a semiconductor substrate is provided with at least one set of alternating conductor and insulator layers formed thereon. An etch is then performed through the at least one set of alternating conductor and insulator layers to form an aperture. An etch resistant layer is formed on the area exposed from the previous etch at the base of the aperture. An etch is performed forming the electron emitter in the one face aligned to the exposed area. The emitter is thereby self-aligned to the overlying conductor and insulator layers. The conductor and insulator layers need not be aligned to an underlying emitter.

Abstract: A multi-poly spacer, double-plate, stacked capacitor or MDSC using a modified stacked capacitor storage cell fabrication process. The MDSC is made up of a rectangular boxed-shaped polysilicon storage node structure, having multiple poly post residing in a buried contact used to connect the MDSC to an active area. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed MDSC. Developing the MDSC from a planarized surface allows the capacitor to be fabricated with only 2 photomask steps. With the 3-dimensional shape and a texturized surface of a polysilicon storage node plate, substantial capacitor plate surface area of 100% or more is gained at the storage node.

Abstract: Local interconnect is defined in a polycrystalline silicon layer. Openings to underlying conducting regions are made through an insulating layer after the local interconnect conductor definition. A thin extra polycrystalline silicon layer is then deposited over the device and etched back to form polycrystalline silicon sidewall elements. These sidewalls connect the polycrystalline silicon local interconnect conductors to the underlying conductive regions. Standard silicidation techniques are then used to form a refractory metal silicide on the exposed underlying conductive regions, the polycrystalline silicon sidewall elements, and the polycrystalline silicon local interconnect conductors. This results in a complete silicided connection between features connected by the local interconnect conductors.

Abstract: A double dynamic random access memory (DRAM) cell comprising two vertically stacked access transistors and storage capacitors. A first access transistor is formed on a silicon substrate. A seed contact to the first access transistor is then utilized for growing an intermediate silicon substrate by Confined Lateral Selective Epitaxial Overgrowth (CLSEG). A second access transistor is formed upon the intermediate silicon substrate. A storage capacitor for the first access transistor may be formed as a trench capacitor in the silicon substrate. A storage capacitor for the second access transistor may be stacked on the second access transistor. A common buried bit line connects the two access transistors.

Abstract: A semiconductor device having a heterojunction and utilizing a two-dimensional electron gas formed at said the heterojunction comprises a substrate of a semi-insulating material, a first semiconductor layer of undoped indium gallium arsenide formed on the substrate, a second semiconductor layer of n-type indium aluminium arsenide formed on the first semiconductor layer and defining the heterojunction between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer including an exposed region defining an exposed top surface, a third semiconductor layer of n-type gallium arsenide antimonide formed on the second semiconductor layer and having a window defined therein so as to expose the top surface of the exposed top surface region, a gate electrode formed in self-alignment with the window and in contact with the exposed top surface region of the second semiconductor layer, and ohmic electrodes formed on the cap layer in ohmic contact therewith.

Abstract: The present invention provides a method for manufacturing a field effect transistor which overcomes problems occurring in the manufacture of InP material junction field effect transistors. Because the electron saturation velocity is higher than that of silicon or GaAs it is desirable to have a gate length shorter than the mask length as well as to have the source, drain, and gate metals evaporated by the self-aligned method. The present invention provides a method of achieving gate lengths of 1 .mu.m or shorter without requiring an expensive electron beam apparatus or X-ray lithography apparatus.

Abstract: The present invention provides a method for manufacturing a field effect transistor which overcomes problems occurring in the manufacture of InP material junction field effect transistors. Because the electron saturation velocity is higher than that of silicon or GaAs it is desirable to have a gate length shorter than the mask length as well as to have the source, drain, and gate metals evaporated by the self-aligned method. The present invention provides a method of achieving gate lengths of 1 .mu.m or shorter without requiring an expensive electron beam apparatus or X-ray lighography apparatus.

Abstract: The sub-micron bipolar devices with method for forming sub-micron contacts provides a sub-micron bipolar device and process for manufacturing it with contacts down to 0.1 microns or less. All processes and devices utilize doped polysilicon as the electrodes for the device elements, and the preferred embodiment surrounds the polysilicon contacts with low temperature oxide covered by SOG to avoid all oxidation steps which otherwise might be detrimental to the extremely thin whisker contacts.

Abstract: A mushroom double stacked capacitor (mushroom cell) using a modified stacked capacitor storage cell fabrication process. The mushroom cell is made up of polysilicon structure, having a mushroom extended V-shaped cross-section. The storage node plate of the mushroom cell is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The shape of the polysilicon structure increases storage capability 200% or more without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.

Abstract: The present invention provides a semiconductor device, comprising a substrate, a first insulation layer formed on the substrate, a first wiring layer formed on the first insulation layer, a second insulation layer formed on the first wiring layer and having a contact hole, and a third insulation layer formed on the second insulation layer, said third insulation layer being in contact with the first wiring layer via the contact hole.

Abstract: In a manufacturing method for a dynamic random access memory with box-structured memory cells is disclosed, a polysilicon side wall is again formed inside the polysilicon side wall forming the outer wall. After that, with the side wall formed on this inner wall used as mask, an opening for forming a cavity is made in the center of the storage node in a self-aligned manner.

Abstract: An improved semiconductor AC switch is described having internal bias generation for the power MOSFET switches and isolated control input. Dual power MOSFETS with substrate diodes are connected in series between source and load. DC gate bias for the MOSFETS is derived from an internal power supply containing energy storage which charges from the line, typically every half cycle. The gates of the power MOSFETS are tied to the internal bias generator through a voltage divider network containing a variable resistance controlled by an optical input signal. The internal energy storage may be a capacitor or solid state battery, preferably a monolithic thick or thin film battery. No transformers or external control bias generators are required and the resulting switch is particularly simple and compact.

Abstract: A method of manufacturing a semiconductor device includes forming desired semiconductor elements in a major surface region of a semiconductor substrate, and ion-implanting a selected element into the semiconductor substrate from the major surface of the substrate to form an ion-implanted layer by the implanted element. A heat treatment is performed to the ion-implanted substrate, causing the ion-implanted layer to getter contaminant heavy metals.

Abstract: A novel process is provided for fabricating contacts (46s, 40g, 46d) in a novel, completely self-aligned, planarized configuration for EPROM elements (66). The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 .mu.m and lower. The EPROM element comprises source (18) and drain (20) regions separated by a gate region (22) and is characterized by the gate region comprising two separate gates, a floating gate (40g) and a control gate (58), capacitively coupled together. The floating gate is formed on a gate oxide (38) over the substrate (16) and the gates are separated from each other and from the source and drain contacts by a dielectric (56). The EPROM element has two threshold voltages, one related to the operation of a "normal" MOS transistor and the other related to a "programmed" threshold, following programming of the transistor. Sensing the threshold voltage of the device permits a determination to be made whether the device is programmed.

Abstract: In a self-alignment type-lateral bipolar transistor and a manufacturing method thereof, the base width is determined not by the image resolution limit of the lithography technique, as in the prior art, but by the impurity diffusion from the polysilicon layer 118. Therefore, the self-alignment type lateral-structure pnp bipolar transistor and the manufacturing method permit the base width to be as small as possible, resulting in improvement of frequency characteristics, and reducing the size of the transistor element.