Patents Examined by Loc Q. Trinh
  • Patent number: 5081062
    Abstract: A semiconductor heterostructure includes separate, device quality regions of gallium arsenide and silicon layers on an insulating substrate such as aluminum oxide or silicon dioxide. The separate regions can be electrically isolated except for intended connections, permitting the fabrication of interrelated gallium arsenide and silicon semiconductor active devices on a single substrate. The device quality gallium arsenide is grown overlying the specially treated device quality silicon layer, by depositing a thin transition layer of gallium arsenide in low temperature growth, annealing it by solid phase epitaxy, and then depositing at a higher temperature a thicker epitaxial layer of gallium arsenide overlying the transition layer.
    Type: Grant
    Filed: June 14, 1989
    Date of Patent: January 14, 1992
    Inventors: Prahalad Vasudev, Irnee J. D'Haenens
  • Patent number: 5075247
    Abstract: A non-volatile, static magnetic memory device, whose operation is based on the Hall effect, is disclosed. The device includes a magnetic patch which stores data in the form of a magnetic field, a semiconductor Hall bar and a pair of integrally-formed bipolar transistors used for amplifying and buffering the Hall voltage produced along the Hall bar. Current is forced to flow down the length of the Hall bar causing a Hall voltage to be developed in a direction transverse to the direction of both the magnetic field and the current. The bases of the bipolar transistors are ohmically coupled to the Hall bar to sense the Hall voltage--the polarity of which is representative of the stored information. A system of current carrying conductors is employed for writing data to individual magnetic patches.
    Type: Grant
    Filed: January 11, 1991
    Date of Patent: December 24, 1991
    Assignee: MicroUnity Systems Engineering, Inc.
    Inventor: James A. Matthews
  • Patent number: 5070028
    Abstract: A method for manufacturing a heterobipolar transistor having and at least greatly diminished extrinsic base-collector capacitance provides an insulation implantation in a sub-collector layer grown onto a semi-insulating substrate via a first mask that covers a region provided for the sub-collector to be constructed or the sub-collector is formed by doping the semi-insulating substrate through a mask. The semiconductor layers for the collector, the base and the emitter, the sub-collector being fashioned in a limited region provided therefore and the emitter is aligned on the sub-collector with a second mask.
    Type: Grant
    Filed: April 1, 1991
    Date of Patent: December 3, 1991
    Assignee: Siemens Aktiengesellschaft
    Inventors: Helmut Tews, Hans-Peter Zwicknagl