Abstract: A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.

Abstract: A magnetic memory device includes a stacked structure including a magnetic element, a protective insulating film covering the stacked structure, and an interface layer provided at an interface between the stacked structure and the protective insulating film. The interface layer contains a predetermined element which is not contained in the magnetic element or the protective insulating film.

Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

Abstract: An organic light-emitting display apparatus includes a pixel electrode, a light emission layer over the pixel electrode, an opposite electrode covering the light emission layer, a plurality of upper layers over the opposite electrode, a light-shielding layer over the upper layers.

Abstract: An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package.

Abstract: Disclosed is an AMOLED display panel structure, comprising a plurality of transversely scan lines which extend horizontally, a plurality of data lines which extend vertically and are insulated from the scan lines, switching lines of a same number of the scan lines which extend vertically, a plurality of row driving circuits coupled to the switching lines and a plurality of column driving circuits coupled to the data lines; one switching line is coupled to one scan line, one row driving circuit is coupled to a plurality of switching lines, one column driving circuits is coupled to a plurality of data lines; the row driving circuit and the column driving circuit are located in the lower border frame region; the left, right and upper frame regions are only used for package to achieve the ultra narrow border frames for all three sides of the AMOLED display panel.

Abstract: A semiconductor device includes at least one first gate structure and at least one second gate structure on a semiconductor substrate. The at least one first gate structure has a flat upper surface extending in a first direction and a first width in a second direction perpendicular to the first direction. The at least one second gate structure has a convex upper surface extending in the first direction and a second width in the second direction, the second width being greater than the first width.

Abstract: A hardmask composition may include a solvent and a 2-dimensional carbon nanostructure containing about 0.01 atom % to about 40 atom % of oxygen or a 2-dimensional carbon nanostructure precursor thereof. A content of oxygen in the 2-dimensional carbon nanostructure precursor may be lower than about 0.01 atom % or greater than about 40 atom %. The hardmask composition may be used to form a fine pattern.

Abstract: A method of fabricating a solar cell can include forming a dielectric region on a silicon substrate. The method can also include forming an emitter region over the dielectric region and forming a dopant region on a surface of the silicon substrate. In an embodiment, the method can include heating the silicon substrate at a temperature above 900 degrees Celsius to getter impurities to the emitter region and drive dopants from the dopant region to a portion of the silicon substrate.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

Abstract: An organic light emitting diode display panel, a manufacturing method thereof and a display device are disclosed, for reducing the number of inkjet heads used in inkjet printing or alleviating the swath mura at printing interfaces. The method comprises manufacturing an anode layer, a light emitting layer and a cathode layer on a base substrate, and the method can further comprise manufacturing by an entire-surface coating process a function layer having a first preset thickness between the anode layer and the light emitting layer; and in a first preset region of the function layer that has been manufactured, manufacturing by an inkjet printing process a function layer having a second preset thickness.

Abstract: Some embodiments relate to a silicon wafer having a disc-like silicon body. The wafer includes a central portion circumscribed by a circumferential edge region. A plurality of sampling locations, which are arranged in the circumferential edge region, have a plurality of wafer property values, respectively, which correspond to a wafer property. The plurality of wafer property values differ from one another according to a pre-determined statistical edge region profile.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: An insulated gate power semiconductor device has an (n?) doped drift layer between an emitter side and a collector side. A trench gate electrode has a trench bottom and trench lateral sides and extends to a trench depth. A p doped first protection pillow covers the trench bottom. An n doped second protection pillow encircles the trench gate electrode at its trench lateral sides. The second protection pillow has a maximum doping concentration in a first depth, which is at least half the trench depth, wherein a doping concentration of the second protection pillow decreases towards the emitter side from the maximum doping concentration to a value of not more than half the maximum doping concentration. An n doped enhancement layer has a maximum doping concentration in a second depth, which is lower than the first depth, wherein the doping concentration has a local doping concentration minimum between the second depth and the first depth.

Abstract: A semiconductor apparatus reduces the effect of inductances and induced magnetic fields, and causes a large current to flow from one device to another device. Provided is a semiconductor apparatus comprising a first device of a first region; a second device of a second region; and a connection conductor that electrically connects the first device to the second device. The connection conductor includes current paths that are adjacent and have opposite directions in at least a portion thereof. The connection conductor causes current to flow from the first device to the second device, and causes current to flow in a direction from the second device toward the first device in at least a portion thereof.

Abstract: A semiconductor-based multi-sensor module integrates miniature temperature, pressure, and humidity sensors onto a single substrate. Pressure and humidity sensors can be implemented as capacitive thin film sensors, while the temperature sensor is implemented as a precision miniature Wheatstone bridge. Such multi-sensor modules can be used as building blocks in application-specific integrated circuits (ASICs). Furthermore, the multi-sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. An integrated multi-sensor module that uses differential sensors can measure a variety of localized ambient environmental conditions substantially simultaneously, and with a high level of precision. The multi-sensor module also features an integrated heater that can be used to calibrate or to adjust the sensors, either automatically or as needed.

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.

Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.