Abstract: An array substrate is disclosed, including a thin film transistor including a substrate, a first gate, a first insulating layer, an active layer, a source, a drain, a second and a third insulating layers, and a second gate. The first gate is disposed on the substrate, the first insulating layer is disposed on the first gate and the substrate, and the active layer is disposed on the first insulating layer, the source and the drain disposed on the active layer form a channel with the active layer, the second insulating layer, the third insulating layer, and the second gate are sequentially disposed in the channel region, a distance between an edge of the second insulating layer and the source and the drain is greater than a distance between an edge of the third insulating layer and the source and the drain.

Abstract: A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.

Abstract: An enhancement-mode GaN-based HEMT device on Si substrate and a manufacturing method thereof. The device includes a Si substrate, an AlN nucleation layer, AlGaN transition layers, an AlGaN buffer layer, a low temperature AlN insertion layer, an AlGaN main buffer layer, an AlGaN/GaN superlattice layer, an GaN channel layer, and an AlGaN barrier layer. Both sides of a top end of the HEMT device are a source electrode and a drain electrode respectively, and a middle of the top end is a gate electrode. A middle of the AlGaN barrier layer is etched through to form a recess, and a bottom of the recess is connected to the GaN channel layer. A passivation protective layer and a gate dielectric layer are deposited on the bottom of the recess, and the gate electrode is located above the dielectric layer.

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

Abstract: An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package.

Abstract: An LCD display device and a series connected quantum dot light-emitting device are disclosed. Using N-type charge generation layer and a P-type charge generation layer disposed in a stacked manner, only one pair of electrodes are required to realize a series connection of QLED device and OLED device. The combination of the two types of diode light-emitting devices can overcome their own weakness to form a light-emitting device having narrow full width at half maximum, high color saturation and high luminous efficiency.

Abstract: An electronics assembly includes a cooling chip structure having a target layer and a jet impingement layer coupled to the target layer. The jet impingement layer has one or more jet channels disposed within the jet impingement layer. Further, one or more through substrate vias are disposed within the jet impingement layer, where the one or more through substrate vias are electrically conductive and are electrically coupled to the target layer. A fluid inlet port and a fluid outlet port are fluidly coupled to the one or more jet channels of the jet impingement layer.

Abstract: The invention describes a method of manufacturing an LED module, comprising the steps of providing a translucent encapsulant comprising a number of layers to enclose a number of LEDs of the LED module; modifying the surface structure of an outer surface of a layer to form at least one dense scattering region corresponding to the position of an LED of the LED module; to form at least one sparse scattering region that does not correspond to the position of an LED of the LED module; and to form a transition scattering region between a dense scattering region and a sparse scattering region. The invention further describes an LED module, and a device comprising a device housing and at least one such LED module.

Abstract: A method of manufacturing an organic EL display device according to an embodiment of the present invention includes: forming a plurality of lower electrodes respectively corresponding to a plurality of pixels on a substrate; forming a plurality of banks, which partition the pixels, between adjacent lower electrodes on the substrate; forming an organic material layer on the lower electrodes and the banks; and selectively irradiating the organic material layer on the banks with an energy ray from a direction of a surface of the organic material layer opposite to a surface of the organic material layer in contact with the banks.

Abstract: An OLED display panel and an OLED display apparatus are provided. The OLED display panel includes an array substrate and a cathode plate disposed corresponding to the array substrate. Multiple cathode strips are disposed in parallel on the cathode plate. Each cathode strip is corresponding to a row of pixel regions of the array substrate and used as cathodes of light-emitting units in the row of pixel regions. Multiple cathode switching elements are disposed on the array substrate, a control terminal of each cathode switching element is electrically connected to one corresponding scan line, a first passage terminal of the cathode switching element is connected to a low voltage direct current power supply, and a second passage terminal of the cathode switching element is connected to one corresponding cathode strip. By the above means, the invention can reduce the cathode resistance.

Abstract: A method of manufacturing a light emitting element includes: providing a wafer including: a substrate, and a semiconductor structure; irradiating the substrate with a laser beam to form a plurality of modified regions in the substrate; and subsequently, separating the wafer into a plurality of light emitting elements. Irradiating the substrate with a laser beam includes: performing a first irradiation step comprising irradiating the laser beam along a plurality of first lines that extend in a first direction that is parallel to the first face and that are aligned in a second direction that is parallel to the first face and intersects the first direction, and subsequent to performing the first irradiation step, performing a second irradiation step comprising irradiating the laser beam along second lines that extend in the second direction.

Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.

Abstract: The present invention disclosures a color filter used for a WOLED display apparatus. The color filter includes a red pixel section, a green pixel section, a blue pixel section and a white pixel section. A red photoresist is disposed in the red pixel section, a green photoresist is disposed in the green pixel section, and a blue photoresist is disposed in the blue pixel section. The white pixel section includes a first sub-section, and a red photoresist, a green photoresist or a blue photoresist is disposed in the first sub-section. The present invention further disclosures a WOLED display apparatus including above color filter. The color filter of the present invention can reduce a Y value of chromaticity coordinate of the white pixel. Required brightness of the monochromatic pixels drops at a white image and power consumption is reduced. Accordingly, the life of display devices rises.

Abstract: The present invention provides a manufacturing method of an OLED display panel and an OLED display panel. The manufacturing method of the OLED display panel of the present invention manufactures a metal nano self assembled layer by ink jet printing with a metal nano printing liquid. The metal nano printing liquid comprises metal nanoparticles, a surface tension modifier and a viscosity modifier, wherein the metal nanoparticles are surface-modified metal nanoparticles to inhibit agglomeration of the metal nanoparticles and to enhance a solubility of the metal nanoparticles. With applying the configuration of the metal nano self assembled layer in the OLED element, the overall performance of OLED element can be effectively promoted and the manufacturing method is simple.

Abstract: Disclosed herein is a distributed performance monitor circuit that includes a plurality of performance monitors connected to a cross-trigger network. Each performance monitor corresponds to a respective functional block of a system and includes a counter circuit. The counter circuit includes a programmable time window counter configured to determine an adjustable counting period, and an event counter configured to count a number of occurrences of an event occurring in the respective functional block during the counting period. The cross-trigger network is configured to receive an output trigger signal generated by a performance monitor when the number of occurrences of the event occurring in the corresponding functional block during the counting period is outside of a threshold band for the performance monitor, and send an input trigger signal to the plurality of performance monitors based on receiving the output trigger signal.

Abstract: The present invention provides a manufacturing method of an OLED display panel and an OLED display panel. The manufacturing method of the OLED display panel of the present invention utilizes an inverted OLED element and manufactures an interface modification layer between the cathode of the OLED element and the light emitting layer by ink jet printing with an interface modification printing liquid. The interface modification printing liquid comprises an electron transporting material, metal nanoparticles which are surface-modified, a surface tension modifier and a viscosity modifier. The interface modification layer is a material layer comprising the electron transporting material and the metal nanoparticles. The electron transporting material can enhance the injection and transport of carriers from the cathode. The strong local electric field generated by the metal nanoparticles with the surface plasma resonance can enhance the injection efficiency of the electrons.

Abstract: A memory structure provided by this invention includes a first substrate, a dielectric layer, a bonding pad, and an isolation structure. The first substrate includes a substrate layer and a memory layer. The substrate layer has opposite first and second surfaces, the memory layer is located on the first surface of the substrate layer, and the first substrate includes a bonding pad region. The dielectric layer is disposed on the second surface of the substrate layer. The bonding pad is disposed on the surface of the dielectric layer in the bonding pad region. The isolation structure penetrates through the substrate layer and is disposed at the edge of the bonding pad region and surrounds the substrate layer in the bonding pad region, and the isolation structure is used for isolating the substrate layer in the bonding pad region from the substrate layer at the periphery of the isolation structure.

Abstract: An electronic device can include a semiconductor material and a semiconductor layer overlying the semiconductor material, wherein the semiconductor layer has a greater bandgap energy as compared to the semiconductor material. The electronic device can include a component having a high electrical field region and a low electrical field region. Within the high electrical field region, the semiconductor material is not present. In another embodiment, the component may not be present. In another aspect, a process can include providing a substrate and a semiconductor layer overlying the substrate; removing a first portion of the substrate to define a first trench; forming a first insulating layer within the first trench; removing a second portion of the substrate adjacent to first insulating layer to define second trench; and forming a second insulating layer within the second trench.

Abstract: An embedded electronics package and method of manufacture includes a support substrate, a power semiconductor component coupled to a first side of the support substrate, and a logic semiconductor component coupled to a second side of the support substrate, opposite the first side. A first insulating material surrounds the logic semiconductor component. A logic interconnect layer is electrically coupled to the logic semiconductor component by at least one conductive micro-via extending through a portion of the first insulating material. A power interconnect layer is electrically coupled to the power semiconductor component by at least one conductive macro-via extending through a thickness of the support substrate. The power interconnect layer is thicker than the logic interconnect layer.

Abstract: The present disclosure provides a low-reflection composite electrode including a first metal layer, a first transparent material layer and a second metal layer and a TFT array substrate using the same. The first metal layer, the first transparent material layer and the second metal layer are sequentially stacked. The low-reflection composite electrode has an extremely low reflection rate. In addition, the average reflection rate of the low-reflection composite electrode is lower than 3%, and even lower than 1% within the green light band. If the TFT array substrate is used in AM-OLED and AM-LCD, the gate and/or the source/drain of the TFT array substrate are the low-reflection composite electrodes, so the polarizer in the AM-LED and the low-reflection coating in the AM-LCD become unnecessary. Thus, the production cost can be reduced and the products can have its superiority.