Abstract: A level shifter includes a current mirror configured to receive an input signal in response to a first power voltage and generate an output signal by mirroring a current corresponding to a second power voltage based on a level of the input signal, a first adjusting circuit coupled to an output terminal of the current mirror and configured to adjust a voltage level of the output terminal of the current mirror in response to a bias voltage, and a second adjusting circuit coupled to a power voltage terminal which receives the second power voltage in parallel to the current mirror and configured to adjust the voltage level of the output terminal of the current mirror.

Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).

Abstract: A power amplifier includes a distributor distributing an input first signal to a second signal and a third signal delayed by about 2? degrees (45<?<90) from the second signal, a first amplifier amplifying the second signal and outputting a fourth signal when a first-signal power level is not lower than a first level, a second amplifier amplifying the third signal and outputting a fifth signal when the first-signal power level is not lower than a second level that is greater than the first level, a first phase shifter receiving the fourth signal and outputting a sixth signal delayed by about ? degrees from the fourth signal, a second phase shifter receiving the fifth signal and outputting a seventh signal advanced by about ? degrees from the fifth signal, and a combiner combining the sixth and seventh signals and outputting an amplified signal of the first signal.

Abstract: A drive circuit of a power device, including an internal power supply, a set-side pulse generation circuit and a reset-side pulse generation circuit that are connected to the internal power supply, for generating a set signal and a reset signal respectively upon detecting that a logic input signal changes from a first logic level to a second logic level, or changes from the second logic level to the first logic level, a set-side level shift circuit and a reset-side level shift circuit that respectively level-shift the set signal and the reset signal, a control circuit that turns on and off the power device respectively responsive to the level-shifted set signal and the level-shifted reset signal, and an ensuring circuit that ensures a first state and a second state, in which the power device is respectively off and on, when the logic input signal is at the first logic level and the second logic level.

Abstract: A level shifter includes a latch circuit, an input stage, a driver stage and a control circuit. The latch circuit is configured to generate an output signal according to a signal level at a first drive node and a signal level at a second drive node. The input stage is configured to receive an input signal to adjust a signal level at a connection node. The driver stage is configured to drive the first drive node by coupling the connection node to the first drive node according to a set of control signals. The control circuit is coupled to the input stage and the driver stage. The control circuit is configured to control the driver stage to couple the connection node to the first drive node by adjusting a signal level of each control signal in the set of control signals during a level transition of the input signal.

Abstract: A circuit for providing temperature compensation to a sense signal having a first temperature coefficient includes a temperature compensation circuit receiving a temperature sense signal indicative of a temperature associated with the sense signal where the temperature compensation circuit is digitally configurable by at least one digital signal to generate a compensating impedance signal having a second temperature coefficient. The compensating impedance signal provides an impedance value in response to the temperature sense signal. The compensating impedance signal is applied to modify the sense signal to provide a modified sense signal having substantially zero temperature coefficient over a first frequency range. The circuit further includes an amplifier circuit receiving the modified sense signal and generating an output signal indicative of the sense signal where the output signal has substantially zero temperature coefficient over the first frequency range.

Abstract: In one example, a power-on reset (POR) circuit comprises a first transistor coupled to a voltage source, a control terminal of the first transistor coupled to a non-control terminal of the first transistor via a resistor; a second transistor coupled to the resistor, a control terminal of the second transistor is coupled to a non-control terminal of the second transistor; and a comparator having first and second terminals, the first terminal coupled to the non-control terminal of the first transistor and the second terminal coupled to the voltage source via an offset circuit.

Abstract: Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

Abstract: The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.

Abstract: A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.

Abstract: A comparator circuit with low power consumption and low kickback noise includes a first dynamic comparator and a second dynamic comparator. The first dynamic comparator is a pre-amplifier for the second dynamic comparator. An enable switch which is connected to the first dynamic comparator has a control terminal connected to a resistance device. The resistance device and the enable switch form a RC delay circuit to reduce the kickback noise of the comparator circuit. Since the comparator circuit is composed of dynamic comparators, the power consumption of the comparator circuit is lower.

Abstract: A semiconductor device of embodiments includes a first normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode via a first wiring, a fourth electrode, and a second control electrode, a second normally-off transistor having a fifth electrode, a sixth electrode electrically connected to the third electrode via a second wiring, and a third control electrode, a first diode having a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a capacitor having a first end portion connected to the first anode and the second control electrode and a second end portion.

Abstract: A circuit includes a high voltage (HV) transistor having a first current electrode, a second current electrode, and a control electrode coupled to receive a control signal. The HV transistor is configured and arranged to be non-conductive when the control signal is at a first state and conductive when the control signal is at a second state. A low voltage (LV) transistor is coupled to the first current electrode of the HV transistor. An HV pad is coupled to the second current electrode of the HV transistor. An operating voltage rating of the HV pad exceeds an operating voltage rating of the LV transistor. A secondary electrostatic discharge protection device is coupled between the second current electrode of the HV transistor and a voltage supply terminal.

Abstract: A comparator circuit includes a first comparator, a second comparator and an inverter. The first comparator includes two N-channel metal-oxide-semiconductor (NMOS) transistors, two first P-channel metal-oxide-semiconductor (PMOS) transistors and two second PMOS transistors. A gate of the NMOS transistors respectively receives first and second voltages, and sources of the first PMOS transistors are connected to first and second resistors, respectively. The first comparator outputs differential output signals from drains of the NMOS transistors according to the voltage difference between the first and second voltages. An output of the second comparator is connected to gates of the first PMOS transistors of the first comparator. An input of the inverter is connected to the output of the second comparator, and an output of the inverter is connected to gates of the PMOS transistors.

Abstract: A pulse generation circuit has: an edge detector detecting a pulse edge in an input signal to generate edge detection signals; a clock generator generating a clock signal according to the edge detection signals; a frequency divider dividing the frequency of the clock signal to generate a frequency-divided clock signal; an input pad for receiving a test mode switch signal from a tester; and an output pad for outputting the frequency-divided clock signal to the tester. The edge detector can generate the edge detection signals by detecting a pulse edge not in the input signal but in the clock signal or in the inverted clock signal obtained by inverting the logic level of the clock signal when the test mode switch signal is being fed in. The signal delay time in the edge detector is adjustable according to the period of the frequency-divided clock signal as measured by the tester.

Abstract: A level shifting circuit includes a level shifting portion configured to receive an input signal and generate an output signal, and a current adjustment circuit connected between the level shifting portion and a drive high voltage node at which a drive high voltage is applied. The current adjustment circuit is configured to adjust an amount of current provided from the drive high voltage node to the level shifting portion.

Abstract: A signal converter, a duty-cycle corrector, and a differential clock generator are provided. The differential clock generator includes the signal converter and the duty-cycle corrector. The signal converter is capable of calibrating skew distortion, and the duty-cycle corrector is capable of calibrating duty-cycle distortion. With the signal converter and the duty-cycle corrector, the differential clock generator can be applied to communication devices operating at high frequency.

Abstract: A drive circuit drives switches that are connected to each other in parallel. The drive circuit includes individual discharge paths, a common discharge path, blocking units, a discharge switch, off-holding switches, and a drive control unit. The drive control unit selects, as target switches to be driven to be turned on, at least two switches among the switches. The at least two switches include a first switch and a second switch. The first switch is last to be switched to an off-state among the at least two switches that are selected as the target switches and switched to an on-state. The second switch is other than the first switch among the at least two switches. The off-holding switches includes a first off-holding switch and a second off-holding switch. After switching the second off-holding switch to an on-state, the drive control unit switches the discharge switch to an on-state.

Abstract: An output circuit may be provided with: input and output terminals; a ground terminal shared by both an input side and an output side; a first switching element of n-channel type having first positive and negative electrodes, and a first gate; a second switching element of the n-channel type having second positive and negative electrodes, and a second gate; a diode; and a resistive element; in which the first positive electrode is connected with a power source, the first negative electrode is connected with the output terminal, anode of the diode is connected with the first negative electrode, cathode of the diode is connected with the first gate, the resistive element is connected between the source and the first gate, the second positive electrode is connected with the first gate, the second negative electrode is connected with the ground terminal, and the second gate is connected with the input terminal.

Abstract: Methods, systems, and apparatus to correct gate bias for a diode-connected transistor are disclosed. An example apparatus includes a first resistor including a first resistor terminal and a second resistor terminal; a second resistor including a first resistor terminal and a second resistor terminal; a first transistor including a current terminal and a gate terminal, the current terminal of the first transistor coupled to the first resistor terminal of the first resistor and the gate terminal of the first transistor is coupled to the second resistor terminal of the first resistor; and a second transistor including a first current terminal and a second current terminal, the first current terminal of the second transistor coupled to the gate terminal of the first transistor, and the second current terminal of the second transistor coupled the first current terminal of the second resistor.