Abstract: A receiver includes a low-side buffer having an input terminal coupled to receive an input signal and having an output terminal coupled to a buffer terminal. Responsive to the input signal being LOW, the low-side buffer is configured to couple the buffer terminal to ground. The receiver also includes a high-side buffer having an input terminal coupled to receive the input signal and having an output terminal coupled to the buffer terminal. Responsive to the input signal being HIGH, the high-side buffer is configured to provide an I/O voltage at the buffer terminal. The receiver also includes an output stage coupled to the buffer terminal and having a low voltage terminal configured to receive a low supply voltage. The output stage is configured to provide an output signal responsive to the I/O voltage at the buffer terminal, wherein the output signal is lower than the I/O voltage.

Abstract: A voltage-current conversion circuit includes a voltage-current conversion resistor connected to an input terminal, and a current mirror circuit which mirrors a current supplied from the voltage-current conversion resistor, wherein the current mirror circuit is constructed to include a depletion-type transistor whose source voltage is biased to be higher than the substrate voltage.

Abstract: A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.

Abstract: A level shifter includes: a first inverter suitable for inverting a signal of a first node based on a first pull-up voltage and a first pull-down voltage; a second inverter suitable for inverting the signal of the first node based on a second pull-up voltage and a second pull-down voltage; and a capacitor coupled between an output node of the first inverter and an output node of the second inverter.

Abstract: In a first aspect, the subject invention provides a variable-intensity light emitting diode (LED) module which includes: a first LED string having first and second ends, the first end being connected to a positive voltage terminal which is connectable to a positive voltage input of a direct current voltage source; a first terminal connected to a first resistor which is connected to the second end of the first LED string; and, a second terminal connected to a second resistor which is connected to the second end of the first LED string. The first and second resistors have different resistances. A negative voltage input of the direct current voltage source is selectively connectable to one of the first and second terminals, whereby, the intensity of light generated by the first LED string is determined by which of the first and second terminals is connected to the negative voltage input.

Abstract: A load control device for controlling the amount of power delivered to an electrical load (e.g., an LED light source) includes first and second semiconductor switches, a transformer, a capacitor, a controller, and a current sense circuit operable to receive a sense voltage representative of a primary current conducting through to a primary winding of the transformer. The primary winding is coupled in series with a semiconductor switch, while a secondary winding is adapted to be operatively coupled to the load. The capacitor is electrically coupled between the junction of the first and second semiconductor switches and the primary winding. The current sense circuit receives a sense voltage and averages the sense voltage when the first semiconductor switch is conductive, so as to generate a load current control signal that is representative of a real component of a load current conducted through the load.

Abstract: Provided are embodiments for a system including a zero-cross circuit. The system includes a first channel and a second channel Each channel includes a generator, a generator relay, and a bus tie relay. In addition, the system includes a zero-cross circuit, wherein the zero-cross circuit synchronizes the operation of the first and second channel, and at least one controller configured to control the operation of the first channel and the second channel based on an input from the zero-cross circuit. Also provided is a method for operating the zero-cross circuit with low phase delay. The method includes receiving an inverting input, receiving a non-inverting input, and comparing the inverting input and the non-inverting input. The method also includes receiving feedback from an output of the comparator; and outputting a waveform based on the comparison of the inverting input and the non-inverting input and the feedback.

Abstract: A level shift circuit includes a complementary signal generating unit, a high voltage pulse generating unit, and a shift and latch unit. The high voltage pulse generating unit is connected to the complementary signal generating unit and the shift and latch unit. The complementary signal generating unit is used to receive a target signal at a low voltage domain and output a complementary signal of the target signal and the target signal. The high voltage pulse generating unit is used to generate a high voltage pulse according to the target signal and complementary signal. The shift and latch unit is used to shift the target signal from the low voltage domain to a high voltage domain when a high voltage pulse is generated, and is used to latch and output the target signal at the high voltage domain.

Abstract: A power converter having fast transient response is provided. The power converter includes a voltage detector circuit and a compensator circuit. The voltage detector circuit includes a plurality of resistors, a plurality of comparators, and a detection control circuit. The resistors are connected in series with each other and grounded. First and second terminals of one of the resistors are respectively connected to a reference voltage and a first terminal of the adjacent resistor. First and second terminals of another of the resistors are respectively connected to a second terminal of the adjacent resistor and grounded. First input terminals of the comparators are respectively connected to second terminals of the resistors. The detection control circuit outputs control signals according to comparison signals. The compensator circuit outputs a compensating signal according to the control signals. A main control circuit controls switch circuits according to the compensating signal.

Abstract: A lighting driver for driving a light-emitting component at a high speed is provided. A control terminal of a second transistor is connected to a control terminal and a first terminal of a first transistor. Input terminals of an operational amplifier are connected to the first terminal of the first transistor and first terminals of first and second switches. Control terminals of third and fourth transistors are connected to an output terminal of the operational amplifier. Second terminals of the first switch and the fourth transistor are connected to a first terminal of the second transistor. A second terminal of the second switch and a current source are connected to a second terminal of the third transistor. A first terminal of the fourth transistor is connected to the light-emitting component. A control circuit is connected to the current source, and control terminals of the first and second switches.

Abstract: Bias circuit and a bias generator circuit comprising such a bias circuit. The bias circuit (10, 11) comprises a switched capacitor resistor circuitry (C1, C2, M12-M17), and an operational amplifier (M1-M4, M10) with an input differential transistor pair (M1, M2). The bias circuit further comprises additional source follower transistors (M5, M6) associated with the first and second input differential transistors (M1, M2). The bias generator circuit has a PMOS switched capacitor reference circuit (11) and a NMOS switched capacitor reference circuit (10) and a transconductor reference cell (15). The transconductor reference cell (15) is a replica of a basic reference cell used in a further circuit.

Abstract: A level shifter for outputting an output voltage having a voltage level range different from a voltage level range of a received input voltage is disclosed. The level shifter includes: a current mirror configured to copy a reference current flowing through a first mirror transistor to a second mirror transistor; a current mirror control circuit electrically connected to the current mirror by a sink node and including a plurality of control transistors configured to control the current mirror; and an output circuit configured to output an output voltage based on a voltage level of the sink node, wherein a first control transistor of the plurality of control transistors receives the output voltage fed back to a gate terminal of the first control transistor, and a second control transistor of the plurality of control transistors receives an inverted output voltage fed back to a gate terminal of the second control transistor.

Abstract: A low noise amplifier includes at least two variable gain amplifier stages, each variable gain amplifier configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to each variable gain amplifier stage, wherein each bandpass filter includes a resonant tank, each resonant tank including an inductor, wherein each inductor of each resonant tank is oriented in orthogonal relation with respect to each respective longitudinal axis of each next inductor, the orthogonal relation of the respective longitudinal axes configured to reduce mutual coupling between the tunable bandpass filters; a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component as a function of a load driving signal; and, a controller circuit configured to tune each tunable bandpass filter.

Abstract: Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement of transistors is opposite the second series arrangement of transistors. The output of the first series arrangement of transistors is coupled to a first node and selectively couples the first node to a first voltage based on an input signal. The output of the second series arrangement of transistors is coupled to a second node and couples the second node to the first voltage based on an input signal. The first node and the second node are coupled to the first voltage at different times. The series arrangements of transistors enables faster level shifting over conventional level shifters.

Abstract: A DC-coupled buffer is provided with two switch transistors controlled by a delayed version of an output signal for the DC-coupled buffer. A first one of the switch transistors functions to cut off a current discharged into ground that would otherwise flow while an input signal for the DC-coupled buffer is discharged. A remaining second one of the switch transistors functions to increase the operating speed of the DC-coupled buffer.

Abstract: The present invention discloses a hysteresis comparator comprising an input stage, a hysteresis current generating circuit and an output stage. In the operation of the hysteresis comparator, the input stage is configured to receive a pair of differential input signals to generate at least one differential current signal; the hysteresis current generating circuit is configured to generate at least one hysteresis current to adjust the differential current signal to generate an adjusted differential current signal, wherein the hysteresis current generating circuit includes a common mode voltage detecting circuit for detecting a common mode voltage of the differential input signal for generating the hysteresis current; and the output stage is configured to generate an output signal according to the adjusted differential current signal.

Abstract: The present disclosure provides bandgap reference circuits having multi-level chopping actions to current mirror circuits for the purpose of reducing the flicker noise of the output reference voltage. A bandgap reference circuit includes a first current mirror including a pair of a first MOSFET and a second MOSFET, a second current mirror comprising a third MOSFET electrically connected to the first current mirror, and configured to provide a reference voltage at a drain, a first bipolar junction transistor electrically connected to the first current mirror, a second bipolar junction transistor connected to the first current mirror via a first resistor, a third bipolar junction transistor connected to the third MOSFET via a second resistor. The bandgap reference circuit further includes an operational amplifier to control the MOSFETs and a plurality of chopping switches configured to perform chopping actions on outputs of the first current mirror and the second current mirror.

Abstract: A hybrid drive circuit (100, 100?) drives a first characteristic transistor and a second characteristic transistor coupled in parallel to the first characteristic transistor according to an input signal (Sin). The hybrid drive circuit (100, 100?) includes a first turn-on path (Pc1), a first turn-off path (Ps1), a second turn-on path (Pc2), and a second turn-off path (Ps2). The first turn-on path (Pc1) and the second turn-on path (Pc2) produce a first delay time to delay turning on the first characteristic transistor. The first turn-off path (Ps1) and the second turn-off path (Ps2) produce a second delay time to delay turning off the second characteristic transistor.

Abstract: A voltage detector detects a voltage of a positive electrode of a battery, and outputs a detection value indicating a detected voltage value. A target voltage to be detected is applied to one end of a resistor, via a first switch. A current is input to an output circuit from the other end of the resistor. The output circuit outputs a current whose current value substantively coincides with the current value of the current input from the resistor to one end of a resistor, while maintaining a voltage value of the other end of the resistor substantively at a predetermined voltage value. A voltage value of the one end of the resistor is output to a microcomputer as the detection value.