Abstract: A voltage detector detects a voltage of a positive electrode of a battery, and outputs a detection value indicating a detected voltage value. A target voltage to be detected is applied to one end of a resistor, via a first switch. A current is input to an output circuit from the other end of the resistor. The output circuit outputs a current whose current value substantively coincides with the current value of the current input from the resistor to one end of a resistor, while maintaining a voltage value of the other end of the resistor substantively at a predetermined voltage value. A voltage value of the one end of the resistor is output to a microcomputer as the detection value.

Abstract: The present application provides a square wave generating method, applied in a square wave generating circuit, configured to generate a mimetic square wave signal, wherein the square wave generating circuit has a breakdown voltage. The square wave generating method comprises the square wave generating circuit generating the mimetic square wave signal as a first voltage during a first time interval; the square wave generating circuit generating the mimetic square wave signal as a second voltage during a second time interval; and the square wave generating circuit generating the mimetic square wave signal as a transient voltage during a transient interval between the first time interval and the second time interval, wherein the transient voltage is between the first voltage and the second voltage; wherein a first voltage difference between the first voltage and the second voltage is greater than the breakdown voltage.

Abstract: Provided is an ambient temperature estimating device, ambient temperature estimating method, program, and system that are able to realize both high robustness and high ambient temperature estimation accuracy. An ambient temperature estimating device includes a neural network, a temperature acquisition unit configured to acquire one or more temperature values inside the ambient temperature estimating device, and a neural network calculator configured to estimate an ambient temperature around the ambient temperature estimating device using the neural network. Input values inputted to the neural network by the neural network calculator include the temperature values acquired by the temperature acquisition unit and a heat source control value for controlling a heat source inside the ambient temperature estimating device.

Abstract: A voltage converter includes a first to a third capacitor, a supply terminal, a first and a second clock terminal and a transfer arrangement, wherein a first electrode of the first capacitor is connected to the first clock terminal and a second electrode of the first capacitor is connected to a first node of the transfer arrangement, wherein a first electrode of the second capacitor is connected to the second clock terminal and a second electrode of the second capacitor is connected to a second node of the transfer arrangement, and wherein a first electrode of the third capacitor is permanently and directly connected to the second electrode of the first capacitor and a second electrode of the third capacitor is connected to a third node of the transfer arrangement.

Abstract: A method of controlling a power supply electrically coupled to a dimmer and a light source includes receiving a plurality of sample values corresponding to dimmer levels, comparing a sample value of the plurality of sample values with one or more inflection points, the one or more inflection points being associated with a plurality of slew-rates, identifying a particular slew-rate among the plurality of slew-rates based on the comparison, and generating a control signal based on the particular slew-rate for transmission to the power supply.

Abstract: A logarithmic amplifier includes a logarithmic current preamplifier circuit and logarithmic amplifier circuit. The logarithmic current preamplifier circuit includes an inverting input terminal, an output terminal, and a first diode. The first diode is coupled between the inverting input terminal of the logarithmic current preamplifier circuit and the output terminal of the logarithmic current preamplifier circuit. The logarithmic amplifier circuit includes an inverting input terminal, an output terminal, and a second diode. The inverting input terminal of the logarithmic amplifier circuit is coupled to the output terminal of the logarithmic current preamplifier circuit. The second diode is coupled between the inverting input terminal of the logarithmic amplifier circuit and the output terminal of the logarithmic amplifier circuit.

Abstract: A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

Abstract: An automatic frequency modulation circuit and an automatic frequency modulation method using efficiency statistics as a reference for frequency modulation applied to a pulse-width modulation (PWM) system are disclosed. The automatic frequency modulation circuit includes an oscillator unit, an on-time generating unit, a frequency adjusting unit and a frequency selecting unit. The oscillator unit receives a reference current and generate a clock signal. The on-time generating unit, coupled to the oscillator unit, receives a reference voltage and a first voltage of the oscillator unit and generates an on-time signal. The frequency adjusting unit, coupled to the on-time generating unit, receives the on-time signal and a PWM signal and generates a frequency adjusting signal. The frequency selecting unit is coupled to the frequency adjusting unit and automatically adjusts an original frequency according to the frequency adjusting signal to generate an adjusted frequency.

Abstract: A system comprises time-tracking circuitry and phase parameter generation circuitry. The time-tracking circuitry is operable to generate a time-tracking value corresponding to time elapsed since a reference time. The phase parameter generation circuitry operable to: receive the time-tracking value; receive a control signal that conveys a frequency parameter corresponding to a desired frequency of an oscillating signal; and generate a plurality of phase parameters used for generation of an oscillating signal, wherein the generation of the plurality of phase parameters is based on the time-tracking value and the frequency parameter such that the oscillating signal maintains phase continuity across changes in the frequency parameter.

Abstract: Example MOSFET circuits include a first metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate, a source and a drain, and a second MOSFET coupled in series with the first MOSFET. The second MOSFET has a gate, a source and a drain. The MOSFET circuit also includes a controller configured to supply a same control signal to the gate of the first MOSFET and the gate of the second MOSFET to turn on or turn off the first MOSFET and the second MOSFET when a drain-source voltage of the first MOSFET and a drain-source voltage of the second MOSFET are substantially zero. Other MOSFET circuits and methods of operating MOSFET circuits are also disclosed.

Abstract: A bias circuit includes first and second bipolar transistors, first and second field-effect transistors, and a filter circuit. The first field-effect transistor supplies a bias signal to an amplifier. The filter circuit is connected between a collector terminal of the first bipolar transistor and the ground through a base terminal of the first bipolar transistor. The filter circuit has frequency characteristics for attenuating a high frequency component of an RF signal to be input to the amplifier.

Abstract: A glitch removal circuit removes glitch noise contained in a Power-good signal and a Power-on Reset signal, and includes: a first glitch removal unit that operates according to a first clock signal, and removes glitch noise from a Power-good signal; and a second glitch removal unit that operates according to a second clock signal, and removes glitch noise from a Power-on Reset signal, in which the first glitch removal unit is configured so as to be initialized according to an output signal of the second glitch removal unit, and the second glitch removal unit is configured so as to be initialized according to an output signal of the first glitch removal unit.

Abstract: An example current mirror arrangement includes a first portion and a second portion, each of which includes a current mirror having transistors Q1 and Q2, a buffer amplifier that has an input coupled to a base/gate terminal of Q1 and an output coupled to a base/gate terminal of Q2, a master resistor coupled to an emitter/source terminal of Q1, and a slave resistor coupled to an emitter/source terminal of Q2. Furthermore, the slave resistor of the first portion is coupled to the slave resistor of the second portion. Providing additional resistors on master and slave sides of a current mirror arrangement may advantageously allow benefiting from the use of buffers outside of a feedback loop of a current mirror while reducing the sensitivity of the current mirror arrangement to buffer offsets.

Abstract: A drive circuit of a power device, including a set-side level shift circuit that receives a set signal and generates a level-shifted set signal, a reset-side level shift circuit that receives a reset signal and generates a level-shifted reset signal, a control circuit that is connected to the set-side level shift circuit and the reset-side level shift circuit, and that outputs a drive signal, a level of the drive signal changing between a first logic level for turning off the power device based on the level-shifted reset signal and a second logic level for turning on the power device based on the level-shifted set signal, and an ensuring circuit that ensures, based on the drive signal, that the control circuit controls to turn on the power device responsive to the level-shifted set signal, and to turn off the power device responsive to the level-shifted reset signal.

Abstract: A system includes a pseudo-differential clock path configured to convey a first clock signal and a second clock signal, wherein the second clock signal is inverted relative to the first clock signal. The system also includes a sensing circuit coupled to sensing nodes of the pseudo-differential clock path. The sensing circuit is configured to provide a sense signal based on a comparison of the first clock signal and the second clock signal at the sensing nodes. The system also includes a correction circuit coupled to the sensing circuit and to adjustment nodes of the pseudo-differential clock path. The correction circuit is configured to adjust the first clock signal and the second clock signal using digital-to-analog converters (DACs) and the sense signal.

Abstract: A clock glitch detection circuit includes a detection circuit and a logic circuit. The detection circuit is configured to receive a clock input signal and a clock output signal and determines whether the clock input signal and the clock output signal are in phase, so as to output a first detection signal and a second detection signal. The logic circuit is coupled to the detection circuit and configured to receive the first detection signal and the second detection signal. The logic circuit determines whether the first detection signal and the second detection signal are in phase, so as to generate a glitch detection signal. The glitch detection signal is configured to indicate whether clock glitch occurs in the clock input signal.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: A power supply voltage monitoring circuit includes a power supply switching circuit, a series circuit including a first series resistor connected to an input power supply line, a second series resistor connected to a ground potential, and a third series resistor connected between the first series resistor and the second series resistor, a first parallel circuit including a first switching element and connected in parallel to the first series resistor, a second parallel circuit including a second switching element and connected in parallel to the second series resistor, a first determination circuit configured to determine whether a first divided voltage between the first series resistor and the third series resistor is in a normal range, and a second determination circuit configured to determine whether a second divided voltage between the second series resistor and the third series resistor is in a normal range.

Abstract: The present disclosure provides implementations of a level shifter (LS), an integrated circuit, and a method. A LS may run in a first mode and a second mode, alternating with each other.

Abstract: An input circuit for detecting low voltage analog signals in an electrically noisy environment receives the analog input signal at an input terminal. The analog input signal is compared to a variable reference signal at a comparator circuit. An active hysteresis circuit provides feedback to the comparator. In a first operating mode, the active hysteresis circuit may be disabled or be configured to output a constant voltage. In a second operating mode, the active hysteresis circuit may be enabled or configured to output a varying level of voltage. The output of the feedback circuit is summed with the variable reference signal and supplied as the input signal to the comparator, such that signal against which the analog input signal is compared is a general constant value in the first operating mode and varies with respect to time in the second operating mode.