Abstract: A switching element driving device includes a main on switch that is connected to gates of a first and second IGBTs and that, when brought into a conductive state, turns on the first and second IGBTs, diodes each disposed between the main on switch and one of the gates of the first and second IGBTs, the diodes having a forward direction from the main on switch to the gates of the first and second IGBTs, an on sub-switch that is connected to the gate of the second IGBT and that, when brought into the conductive state, turns on the second IGBT, and a control circuit that controls the conductive state and a non-conductive state of the main on switch and the on sub-switch.

Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.

Abstract: A driver circuit includes a gate capacitance discharge circuit that reduces a resistance value of a resistor for pulling down the gate of a PMOSFET at the output stage for a predetermined period at the timing when an NMOSFET turns on and a pull-down resistor switching circuit that switches pull-down resistors of the gate capacitance discharge circuit, based on a divided voltage into which voltage of the high voltage power supply system is divided, in which the pull-down resistor switching circuit, when the divided voltage is higher than a reference voltage Vref, switches the pull-down resistor for the predetermined period to a resistor and, when the divided voltage is the reference voltage Vref or lower, switches the pull-down resistor to a resistor having a higher resistance value than the resistor.

Abstract: A power-on reset circuit is provided. During a power-on process of the power-on reset circuit, a threshold voltage of an output signal rstn jumping from a low level to a high level is adjusted by clamp of a voltage at a node c and voltage division between a first resistor and a second resistor, and is controlled to be greater than a threshold voltage of a metal oxide semiconductor device. During a power-off process of the power-on reset circuit, a threshold voltage of the output signal rstn jumping from the high level to the low level is adjusted by increasing a voltage at a node d by means of a third resistor and voltage division between the first resistor and the third resistor, and is controlled to be greater than the threshold voltage of the metal oxide semiconductor device.

Abstract: A pulse modulation circuit with a high-frequency-limiting function, including a comparator, an RS trigger, a switching triode, a NAND gate, a NOR gate, and a charging capacitor. A capacitor charging time is controlled by adjusting a bias current IB1, a bias current IB2, a reference voltage V1, and a reference voltage V2 or adjusting values of capacitors C1 and C2. In this way, a highest output frequency of a pulse generator is limited, so as to reduce hardware system overheads.

Abstract: Devices and methods are provided where a control terminal resistance of a transistor device is set depending on operating conditions within a specified range of operating conditions.

Abstract: Comparison circuit and delay cancellation method are provided. The circuit includes a control circuit, capacitors and a transconductance amplifier circuit, wherein the control unit is configured to receive an input signal and control the comparison circuit to be in different working stages; the capacitors are configured to store a DC offset voltage signal at an automatic zero calibration stage; store the input signal when the output signal is inverted at a measurement stage; and store an equivalent delay voltage signal at a delay sampling stage; the transconductance amplifier circuit is configured to store the DC offset voltage signal to the capacitors at the automatic zero calibration stage; compare voltage signals on positive and negative input terminals and generate an output signal at the measurement stage; and store the equivalent delay voltage signal to the capacitors at the delay sampling stage. An inherent delay of the comparison circuit may be cancelled.

Abstract: A switch circuit includes a first conductive terminal configured to receive a first signal from a first pin of a connector, a second conductive terminal configured to receive a second signal from a second pin of the connector, a third conductive terminal electrically connected to a third pin of the connector, and a fourth conductive terminal electrically connected to a fourth pin of the connector. The third conductive terminal outputs a first power signal of a first voltage level to the third pin of the connector upon receiving the first signal, and the fourth conductive terminal outputs a second power signal of a second voltage level to the fourth pin of the connector upon receiving the second signal.

Abstract: A receiver is provided. The receiver includes a first signal path and a second signal path coupled between an input terminal and an output terminal. A first transistor in the first signal path has a control electrode coupled to a voltage source terminal and a first current electrode coupled at the input terminal. The first transistor is configured and arranged for receiving a first signal at the first input terminal having a voltage exceeding a voltage rating of the first transistor. A second transistor in the first signal path has a first current electrode coupled to a second current electrode of the first transistor and a control electrode coupled to receive a first control signal. The second transistor is configured to form an open circuit in the first signal path when the first control signal is at a first state. A first resistor network in the second signal path is configured and arranged for attenuating the first signal.

Abstract: One illustrative dual mode frequency multiplier embodiment includes: a first and a second nonlinear element, a summation node, and a switchable phase shifter. The first and second nonlinear elements are driven by a differential signal to produce a first and a second branch signal each having even and odd harmonics, the even harmonics being in-phase and the odd harmonics being out of phase. The first and second branch signals combine at the summation node to form a combined signal. The switchable phase shifter couples the first nonlinear element to the summation node, providing the first branch signal with a phase shift switchable between 0 and 180° to suppress either the odd or the even harmonics from the combined signal.

Abstract: A bias circuit includes first and second bipolar transistors, first and second field-effect transistors, and a filter circuit. The first field-effect transistor supplies a bias signal to an amplifier. The filter circuit is connected between a collector terminal of the first bipolar transistor and the ground through a base terminal of the first bipolar transistor. The filter circuit has frequency characteristics for attenuating a high frequency component of an RF signal to be input to the amplifier.

Abstract: A level shifting circuit generates a pulse signal, when both of the logic levels of two complementary input signals of a level shifter has changed while both of the logic levels of two output signals of the level shifter present at low logic level, to pull up either one of the output signals of the level shifter to a second high logic level. Once the logic level of both output signals at the first output node and the second output node present complementary, the level shifting circuit stops pulling up the output signal.

Abstract: A power supply voltage is monitored by a monitoring circuit including a variable current generator and a band gap voltage generator core receiving the variable current and including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the variable current generator generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.

Abstract: A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.

Abstract: The disclosure is directed to a power drop reset circuit which includes not limited to: a first step circuit configured to detect a change of a power supply voltage per unit of time and transmit an enable signal in response to the first step circuit having determined that the change of the power supply voltage per unit of time has dropped below zero, wherein the first step circuit does not consume any current when the Vcc change per unit of time is greater than or equal to zero; and a second step circuit electrically connected to the first step circuit and configured to detect the Vcc in response to having received the enable signal and generate a power drop reset signal in response to having determined that the Vcc has dropped below a predetermined operating voltage, wherein the second step circuit consumes an operating current after receiving the enable signal.

Abstract: A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.

Abstract: Provided is a level shifter which can retain an operation margin and enhance an exceeded-breakdown-voltage preventing effect. The level shifter in an embodiment includes an exceeded-breakdown-voltage prevention circuit between a pair of first-conductivity-type cross-coupled transistors and a pair of second-conductivity-type input transistors. The exceeded-breakdown-voltage prevention circuit includes first-conductivity-type first transistors and second-conductivity-type second transistors which are coupled in series to each other, and first-conductivity-type third transistors coupled in series to the first and second transistors on a higher-potential side.

Abstract: A down-conversion mixer includes a converting-and-mixing module and a load module. The converting-and-mixing module performs voltage-to-current conversion and mixing with first and second differential oscillatory voltage signal pairs upon a differential input voltage signal pair to generate first and second differential mixed current signal pairs. The load module includes two RL circuits and a negative resistance providing circuit that cooperate to convert the first and second differential mixed current signal pairs into first and second differential mixed voltage signal pairs. Each RL circuit includes two variable resistors, and an inductor connected between the variable resistors.

Abstract: This disclosure provides systems, methods and apparatuses for processing analog signals with a wide dynamic range. In some implementations, the analog signal may be a current signal that is logarithmically scaled to decrease its dynamic range and converted to an output voltage using two or more diodes. A first diode may be used to scale a first range of the current signal and a second diode may be used to scale a second range of the current signal.

Abstract: A load control device for controlling the amount of power delivered to an electrical load (e.g., an LED light source) includes first and second semiconductor switches, a transformer, a capacitor, a controller, and a current sense circuit operable to receive a sense voltage representative of a primary current conducting through to a primary winding of the transformer. The primary winding is coupled in series with a semiconductor switch, while a secondary winding is adapted to be operatively coupled to the load. The capacitor is electrically coupled between the junction of the first and second semiconductor switches and the primary winding. The current sense circuit receives a sense voltage and averages the sense voltage when the first semiconductor switch is conductive, so as to generate a load current control signal that is representative of a real component of a load current conducted through the load.